2.2 Copper features and vias

In CAD software, a trace is a perfect vector line with zero resistance and infinite precision. On the factory floor, however, a trace is a physical, three-dimensional copper structure subject to the harsh realities of acid etching, thermal expansion, and electrical resistance. It is not just a visual connection; it is a physical component. Treating copper features merely as abstract drawings often leads to boards that overheat under load, short-circuit, or are unnecessarily expensive to manufacture.

Traces and planes: the horizontal highways

Every piece of copper on a PCB serves one of two distinct purposes: Signal Transmission (carrying data) or Power Distribution (carrying electrical current).

Trace width and spacing

The physical width of a trace dictates how much electrical current it can safely carry before overheating. The spacing (clearance) between traces determines the risk of creating a short circuit during manufacturing.

• The Engineering Reality: Factory machines remove unwanted copper using chemical etching. If traces are placed too close together (typically under 5 mil), the acid baths may fail to clear the copper between them, resulting in a microscopic bridge and a defective board.
• The Current Risk: Designing a trace that is too thin for the amount of current flowing through it will cause the copper to heat up, eventually acting as a physical fuse that burns open.
• The Density Risk: Packing signal traces too tightly together to save space drastically lowers the manufacturing yield due to inevitable acid etching defects.

Pour vs. trace

• Trace: A narrow, highly specific path used for routing a single data signal or a very small amount of power.
• Polygon Pour (Plane): A massive, continuous area of solid copper, typically connected directly to Ground (GND) or a main Power net.
• The Function: Solid copper planes provide a low-resistance path for return currents to flow back to the source, and they act as a highly effective thermal heat sink for hot components.
• Actionable Rule: Ground pours should be maximized on every available layer. A solid, uninterrupted ground plane drastically reduces electromagnetic interference (EMI) emissions and stabilizes the integrity of fast data signals.

Vias: the vertical interconnects

Because a PCB is a 3D structure, signals must move up and down. Vias act as vertical elevators that move signals between different layers. They are created by drilling a tiny hole through the board substrate and chemically treating the walls (plating) to deposit conductive copper.

1. Plated through-hole (PTH)

• Definition: The classic via—a hole drilled completely through the entire thickness of the board, connecting the Top layer straight through to the Bottom layer.
• Use Case: The standard for 95% of layer-to-layer connections. They are incredibly reliable and cost-effective to manufacture.
• The Constraint: A Plated Through-Hole (PTH) via consumes routing space on every single layer of the board, even the inner layers it does not connect to. A signal wire trying to cross Layer 3 is forced to route around the physical barrel of a PTH via passing through it.

2. Blind and buried vias (HDI technology)

• Blind Via: Connects an outer surface layer down to an inner layer (for example, Layer 1 dropping down to Layer 2), without penetrating the rest of the board thickness.
• Buried Via: Connects internal layers to each other (for example, Layer 2 connecting to Layer 3) and remains completely invisible from the outside of the finished board.
• The Engineering Reality: Utilizing these advanced vias requires the factory to perform highly complex sequential lamination steps and use expensive laser drilling machines.
• Actionable Rule: Using Blind or Buried vias will naturally increase the cost of the bare board by 30% to 50%. It is best to use them only when the density of the product (like inside a tightly packed smartphone) explicitly demands it.

3. Via-in-pad

• Definition: The practice of placing a routing via directly inside the copper of a component’s surface-mount solder pad to save space.
• The Risk: During the reflow soldering process, liquid solder will act like water and flow straight down the open hole of the via (a failure known as “wicking”). This starves the pad and leaves the component leg with insufficient solder.
• The Control: To prevent wicking, any via-in-pad must be factory “capped” or completely filled with solid epoxy and then plated flat over the top with copper (a process called Plated Over Filled Via, POFV). This adds significant manufacturing cost to the board.
• Actionable Rule: Leaving via-in-pads open and unfilled to save space guarantees massive, uncorrectable solder joint failures on the assembly line.

The annular ring: accounting for drill drift

A factory drill bit is a long, highly flexible steel tool spinning at incredible speeds. It naturally bends and wanders slightly off-center. The “Annular Ring” is the donut-shaped ring of copper pad that successfully remains surrounding the drilled hole after the machine has passed through.

The drill tolerance reality

Defining a small 0.2 mm hole directly inside a tight 0.25 mm copper pad leaves an incredibly thin annular ring of only 0.025 mm.

• Engineering Reality: Fast mechanical drills on a busy factory floor have a natural wandering tolerance of at least ±0.1 mm.
• The Trap: When a pad is too small to absorb this mechanical drift, the wandering drill will miss the center of the pad and break entirely out of the surrounding copper wall. This defect is called “Breakout,” and it severs the electrical connection from the surface trace to the via barrel.
• Actionable Rule: To ensure reliable manufacturing, verify that the via pad diameter is comfortably larger (at least 0.3 mm) than the specified drill hole diameter.

Pro-Tip: “Teardrops” are an incredibly useful CAD feature that automatically adds extra fillets of copper at the precise junction where a thin trace meets a larger round pad or via. Enabling Teardrops globally in the CAD tool provides mechanical stress relief against vibration and offers a vital safety margin of extra copper against drill breakout.

Final Checkout: Copper features and vias

Feature	Standard Spec	High Cost / High Risk	The Engineering Rule
Trace Width	≥ 6 mil (0.15 mm)	< 4 mil (0.10 mm)	Wider is safer. Only push the limits of thin traces if space density is critical.
Trace Clearance	≥ 6 mil (0.15 mm)	< 4 mil (0.10 mm)	Tighter spacing exponentially increases the risk of acid-etching short circuits.
Via Architecture	Through-Hole Technology (THT)	Blind / Buried (HDI)	Avoid HDI vias unless the board form-factor is too small to fit standard THT.
Annular Ring	+0.3 mm over drill	+0.15 mm over drill	Pad sizes must reasonably account for high-speed mechanical drill wander.
Via-in-Pad	Avoid entirely	Required by BGA	Any via-in-pad must be explicitly requested as “Capped and Plated Over” (POFV) to prevent solder theft during reflow.