2.1 Material Science, Stackups and Via Architecture

A printed circuit board defined solely by Gerber files is an incomplete specification. Without an explicitly documented material and stackup definition, fabrication houses may default to the lowest-cost laminate that meets the bare minimum IPC class. This can result in signal integrity loss, warping during reflow, or Conductive Anodic Filament (CAF) growth causing field failures.

To ensure reliability, the Golden Data Pack should clearly define the physical chemistry and precise geometry of the bare board before a single panel is fabricated.

Material Selection & Thermal Reliability

Selecting laminate materials based solely on the dielectric constant (Dk) is a fundamental error. Laminate materials must be specified based on the thermal stress of the SMT assembly process and the harshness of the operating environment.

The Selection Logic:

When the assembly process is purely Lead-Free (SAC305) requiring multiple reflow cycles, High-Tg material (Tg ≥ 170˚C) must be explicitly specified to prevent Z-axis barrel cracking.
When the PCB operates in high-voltage, high-humidity, or confined environments, Anti-CAF resistant laminates must be required.
When the board requires high-reliability, densely-packed via structures, the Z-axis Coefficient of Thermal Expansion (CTE) must be controlled to ≤ 3.0% (from 50 to 260˚C) to match the physical expansion rates of the plated copper.
When BGA rework is anticipated, the Decomposition Temperature (Td) must be ensured to be ≥ 340˚C to prevent pad delamination during localized hand soldering.

Stackup & Impedance Control

Relying on the fabricator’s internal “standard” stackup for high-speed designs is prohibited. The exact layer buildup must be explicitly defined to control crosstalk, radiated emissions, and signal return paths.

Impedance Models: Clear impedance requirements must be embedded directly into the mechanical fabrication drawing or the ODB++ metadata.
- Single Ended: 50Ω ± 10% (Typical standard)
- Differential Pair: 90Ω or 100Ω ± 10% (Mandatory for USB, PCIe, Ethernet)
Copper Balance: A symmetrical copper distribution around the center of the stackup must be maintained. Uneven copper weights (e.g., pouring 1 oz on L1 but 0.5 oz on L4) can cause “potato chip” warping during reflow, leading directly to SMT placement failures.
Core vs. Prepreg Construction: The exact glass weave must be defined.
- When high-speed signals cross wide gaps in the fiberglass weave, the use of low-Dk spread glass styles (e.g., 1067, 1078) must be specified to minimize fiber weave effect skew.

Pro-Tip: Specifying rigid manufacturer laminate brands (e.g., “Must use Isola 370HR”) must be avoided unless it is chemically critical. Instead, the exact IPC-4101 slash sheet (e.g., “/126”) and the performance parameters must be specified. This allows the fab to utilize equivalent verified stock dynamically without triggering a timeline-delaying Engineering Query (EQ).

Via Architecture & Aspect Ratios

Via reliability is a function of plating bath fluid dynamics and the via Aspect Ratio (Board Thickness ÷ Drill Diameter). Exceeding standard aspect ratios prevents adequate plating solution flow, resulting in thin copper knees and eventual open circuits during thermal expansion.

The Geometric Constraints:

Standard Through-Hole Vias: Aspect Ratio must be limited to 10:1 (e.g., an industry-standard 1.6 mm thick board requires a ≥ 0.16 mm drill bit).
Microvias (Blind): Aspect Ratio must be limited to 0.8:1. Stacked microvias pose a significant reliability risk; Staggered microvias must be utilized wherever possible to reduce stress concentration at the layer interface.
Plating Thickness: IPC Class 2 average (20 µm) or Class 3 average (25 µm) internal copper plating thickness must be required on the Fab Drawing.

Validation & Evidence

Physical evidence from the fabrication house must be required for every production lot to guarantee quality.

1. Impedance Coupons (The TDR Check):

The fab must add test coupons to the sacrificial panel waste rail.

Action: An official TDR (Time Domain Reflectometry) report explicitly matching the coupons to your specific batch serial number must be required.

2. Microsections (Cross-Sections):

Action: The physical acrylic puck or a high-res digital image of the microsection must be requested.
Inspect: Pink ring (chemical delamination), wicking (copper migrating along glass fibers), and the actual measured plating thickness exactly at the hole knee must be checked carefully.

3. Solderability Testing:

Action: The surface finish (ENIG, OSP, HASL) must be ensured to pass physical wetting balance tests to prevent “Black Pad” oxidation or non-wetting issues during SMT assembly.

Final Checkout: Material science, stackups and via architecture

The Control Point	The Operational Requirement
Material Spec	Explicitly define Tg, Td, and the IPC-4101 Slash Sheet.
Impedance	Specify exact Target (Ω) and strict Tolerance (± 10% or ± 5%).
Aspect Ratio	Cap Through-Hole at ≤ 10:1; Blind Microvias at ≤ 0.8:1.
Via Protection	Clearly define Tenting, Plugging, or Filling (e.g., IPC-4761 Type).
Surface Finish	Match the finish to the assembly technology (e.g., ENIG required for Fine Pitch).
Deliverables	Mandate the TDR Report + Microsection Analysis per production lot.
Warp/Bow Limit	Max 0.75% (SMT standard limit) to prevent component placement errors.