Skip to content
Your Bookmarks
    No saved pages. Click the bookmark icon next to any article title to add it here.

    2.1 PCB materials and layers

    The Printed Circuit Board (PCB) is not merely a passive plastic holder for components; it is an active mechanical structure that constantly expands, contracts, and absorbs heat. When the selected substrate material is mismatched to the thermal environment of the manufacturing process, the board can delaminate (tear itself apart) during soldering. The stackup must be designed not just for electrical connectivity, but for mechanical survival.

    The substrate: FR-4 and the “Tg” factor

    Section titled “The substrate: FR-4 and the “Tg” factor”

    The vast majority of modern electronics are built on a substrate called FR-4 (Flame Retardant 4), which is a rigid composite made of woven fiberglass cloth saturated with epoxy resin. This composite acts as the non-conductive mechanical skeleton of the board. However, while “FR-4” is the generic industry category, the most critical explicitly defined specification is the material’s Tg (Glass Transition Temperature).

    It is crucial to understand that Tg is not the melting point. Rather, it is the specific temperature threshold at which the normally rigid epoxy resin becomes soft and rubbery. When the material crosses this thermal threshold, it expands rapidly in the Z-axis (thickness).

    • The Engineering Reality: Modern lead-free soldering processes require reflow oven temperatures to reach up to 260˚C.
    • Standard Tg (130˚C – 140˚C): This is generally acceptable for simple, low-cost consumer electronics that only have a few layers.
    • High Tg (170˚C+): This is highly recommended for industrial equipment, automotive electronics, or any high-density board with 8 or more layers.
    • The Trap: When the resin expands too much during reflow because a Low Tg material was specified for a complex board, the tiny copper barrels plated inside the vias can stretch and fracture (Via Cracking). This causes intermittent open circuits that are notoriously difficult to debug.

    A bare PCB is manufactured by pressing and laminating alternating layers of conductive copper and insulative substrate under intense heat. The “Stackup” is the highly specific and engineered arrangement of these individual layers.

    • Core: This acts as the foundation. It is a rigid, fully cured piece of FR-4 with solid copper foil already permanently bonded to both sides.
    • Prepreg: These are uncured, “sticky” fiberglass sheets used as the binding layer placed between the rigid cores. Inside the lamination press, extreme heat and pressure melt the Prepreg, permanently fusing all the layers together into a solid board.
    • Structure: Top Copper – Solid Core – Bottom Copper.
    • Use Case: Simple, heavily cost-optimized, low-speed circuits (like toys or basic breakout boards).
    • Limitation: A 2-layer board offers zero electromagnetic shielding. Fast signals running on the top layer are highly likely to bleed through and interfere with signals running on the bottom layer.
    • Structure: Top Signal – Continuous Ground Plane – Continuous Power Plane – Bottom Signal.
    • Advantage: The internal, solid sheets of copper act as effective electromagnetic shields. They provide a stable voltage supply to all components and significantly reduce emitted electromagnetic interference (EMI).
    • Actionable Rule: When a design includes any high-speed digital signals (like USB, WiFi, or fast memory), a 4-layer board becomes the minimum requirement to ensure signal integrity.
    • Use Case: Extremely high-density routing (Smartphones, Motherboards, dense computing modules).
    • Cost Driver: Every additional pair of layers requires an entirely new, time-consuming lamination cycle in the factory. Moving a design from 4 layers to 6 layers will often increase the cost of the bare board by 30% to 50%.

    In the PCB industry, copper thickness is traditionally measured in ounces per square foot (oz/ft²), usually just called “ounce copper.” This physical thickness directly dictates how much electrical current the routed traces can safely carry before overheating.

    • 1 oz (35 µm): This is the standard. It provides a balance between decent current-carrying capacity and high-precision chemical etching.
    • 2 oz (70 µm): Used for high-power applications. This should be explicitly specified for heavy motor controllers or main power supplies to handle high-amp loads without overheating the board.
    • 0.5 oz (18 µm): Used for fine-pitch designs. This ultra-thin copper is often required for highly dense digital boards where the traces must be incredibly narrow.

    Heavier, thicker copper is exponentially harder for the factory to etch accurately.

    • The Trap: Specifying thick 2 oz copper to handle power precludes using tiny 4 mil trace widths for data lines on that same layer. The acid in the factory baths cannot etch straight down through that much thick copper without also eating sideways into the trace walls (a defect known as “undercutting”).
    • The Result: Using thick copper forces a significant increase in trace spacing, which drastically reduces the overall routing density of the board.

    ParameterRequirementValue / ConditionAction / Consequence
    Glass Transition Temp (Tg)Must withstand lead-free reflow (~260°C).Standard Tg: 130–140°C (simple, low-layer boards).
    High Tg: ≥170°C (industrial, automotive, or ≥8 layers).
    FAIL: Low Tg for complex boards → via cracking & delamination.
    Layer CountMust ensure signal integrity & EMI control.2-Layer: Simple, low-speed circuits only.
    4-Layer: Minimum for any high-speed signals (USB, WiFi).
    6+ Layers: High-density routing (e.g., smartphones).
    4 layers mandatory for high-speed design. Multi-layer increases cost 30-50% per pair.
    Copper Weight (Thickness)Must meet current capacity & etching feasibility.1 oz (35 µm): Standard balance.
    2 oz (70 µm): High-power circuits (motor controllers).
    0.5 oz (18 µm): Fine-pitch, high-density designs.
    Thick copper (2 oz) forces wider trace spacing, reducing routing density.

    Сообщение об ошибке