4.3 Risk management for EMS projects

In hardware manufacturing, relying solely on optimism is an operational risk. A successful engineering manager systematically identifies and mitigates potential failure modes long before they manifest on the factory floor. Think of risk management not as bureaucratic paperwork, but as the fundamental engineering discipline of anticipating the future. When identified early, a technical or supply risk is a manageable variable. When ignored, it can become a crisis that halts production entirely.

The following framework outlines the six primary areas where hardware projects commonly encounter challenges. Consider this a checklist to guide every design review.

1. Supply chain risk (the components)

The Risk: Being unable to build a product due to missing raw materials.

A production line stoppage is most often caused by a simple, low-cost component—like a $0.05 ceramic capacitor—that suddenly becomes unavailable globally.

Detection: Rigorously check the Bill of Materials (BOM) against live market databases (e.g., SiliconExpert, IHS) to verify the lifecycle status and global inventory of every component.
The Threat: When a critical component, such as a power IC, is “Sole Source” (manufactured by only one vendor), the project’s success becomes entirely dependent on that single supplier’s continued production and delivery.
Mitigation:
- Design Phase: Validate and approve at least two alternate part numbers for every passive component on the board.
- Procurement Phase: Purchase “safety stock” for high-risk, long-lead-time silicon components as soon as the architectural design is approved—even before the PCB layout is finalized.

2. Design risk (the margins)

The Risk: A product that works perfectly on the lab bench suffers high failure rates in the factory environment.

Lab benches use stable power supplies, climate-controlled air, and carefully tuned prototypes. Factories, however, must account for the statistical distribution of component tolerances and environmental variations.

Detection: Require Monte Carlo simulations and Worst Case Circuit Analysis (WCCA) during the schematic design phase.
The Threat: If an analog circuit requires a resistor to stay within a 1% tolerance across all temperatures to function, normal manufacturing variation will inevitably lead to failures on the production line.
Mitigation: Design for wider tolerances. Create robust architectures that continue to function correctly even when underlying component parameters drift by 5% or more over time or temperature.

3. Process risk (the assembly)

The Risk: The physical design exceeds the mechanical capabilities of the factory’s assembly equipment.

Detection: Run a Design for Manufacturability (DFM) report and request the factory’s historical Process Capability Index (Cₚₖ) analysis for similar component footprints.
The Threat: Placing a large BGA processor with a very tight 0.3mm pitch on a surface-mount line calibrated for 0.5mm pitch can cause significant solder bridging under the chip, crashing the first-pass yield (FPY).
Mitigation: Avoid jumping directly to mass production. Instead, conduct a Pilot Build (e.g., 50 units) specifically designed to measure the factory’s Cₚₖ for your exact board layout before committing to high-volume manufacturing.

The Risk: Shipping defective units to customers because the test process could not detect the flaw.

Detection: Perform a rigorous Test Coverage Analysis. Map every physical net on the schematic to a specific, automated verification method.
The Threat: If a critical hardware feature is deemed “untestable”—due to a lack of physical test points or firmware diagnostics—that feature is essentially shipped without any verification.
Mitigation: Incorporate physical copper test points for In-Circuit Testing (ICT) during the PCB layout phase. For complex digital chips, implement Boundary Scan (JTAG) to logically verify solder joints without requiring physical probe access.

5. Compliance risk (the legal wall)

The Risk: The finished product is seized by customs or banned from sale for failing to meet regulatory standards.

Detection: Conduct an early regulatory architectural review targeting relevant directives like FCC, CE, UL, and RoHS.
The Threat: Placing a pre-certified WiFi module next to an unshielded switching power supply can cause the final system to fail radiated emissions testing. This often forces an expensive PCB re-spin and delays the product launch by months.
Mitigation: Perform early “pre-scans” at a certified compliance lab during the prototyping phase. Do not wait until the final product with injection-molded plastics is ready to check for Electromagnetic Interference (EMI).

6. Logistics risk (the physical journey)

The Risk: The hardware survives manufacturing but is damaged during shipping to the customer.

Detection: Conduct aggressive drop testing and simulated vibration profiles on the fully packaged product.
The Threat: Shipping a product designed for bulk pallet transport via a standard courier service (like UPS or FedEx) can result in damage from routine 1-meter conveyor belt drops, potentially shattering internal components like LCDs.
Mitigation: Have an external lab perform ISTA-2A shipping transit tests on the final packaged unit. Consider using single-use “Shock Watch” indicator stickers on outer cartons to detect severe handling events during transit.

Recap: Risk Management for EMS Projects

Risk Area	Key Parameter	Requirement / Criterion	Action / Mitigation
Supply Chain	Component Lifecycle & Inventory	Verify for every BOM line item via live market databases.	Design Phase: Validate ≥2 alternates for all passives. Procurement Phase: Purchase safety stock for high-risk silicon post-architectural approval.
Design	Component Parameter Drift	Design circuits to function correctly with ≥5% tolerance variation.	Perform Monte Carlo & Worst Case Circuit Analysis (WCCA) during schematic design.
Assembly Process	Process Capability (Cₚₖ)	Evaluate for specific component footprints (e.g., 0.3mm pitch BGA).	Conduct Pilot Build (e.g., 50 units) to measure Cₚₖ before mass production.
Testing	Test Coverage	100% of physical nets must map to an automated verification method.	Incorporate ICT test points in PCB layout; implement JTAG/Boundary Scan for complex chips.
Compliance	Regulatory Standards (FCC, CE, UL, RoHS)	Conduct early architectural review for relevant directives.	Perform EMI/EMC “pre-scans” at a certified lab during prototyping.
Logistics	Shipping Durability	Survive standard courier handling (e.g., 1-meter drops).	Perform ISTA-2A transit tests on final packaged unit; use “Shock Watch” indicators.