2.1 Material Science, Stackups and Via Architecture

A printed circuit board defined solely by Gerber files is an incomplete specification. Without an explicitly documented material and stackup definition, fabrication houses may default to the lowest-cost laminate that meets the bare minimum IPC class. This can result in signal integrity loss, warping during reflow, or Conductive Anodic Filament (CAF) growth causing field failures.

To ensure reliability, the Golden Data Pack should clearly define the physical chemistry and precise geometry of the bare board before a single panel is fabricated.

Material Selection & Thermal Reliability

Selecting laminate materials based solely on the dielectric constant (Dk) is a fundamental error. Laminate materials must be specified based on the thermal stress of the SMT assembly process and the harshness of the operating environment.

The Selection Logic:

• For assemblies using a purely Lead-Free (SAC305) process that requires multiple reflow cycles, you should explicitly specify a High-Tg material (Tg ≥ 170˚C). This prevents Z-axis barrel cracking.
• For PCBs that will operate in high-voltage, high-humidity, or confined environments, you must require Anti-CAF resistant laminates.
• For high-reliability boards with densely-packed via structures, the Z-axis Coefficient of Thermal Expansion (CTE) should be controlled to ≤ 3.0% (measured from 50 to 260˚C). This matches the physical expansion rates of the plated copper.
• If BGA rework is anticipated, ensure the Decomposition Temperature (Td) is ≥ 340˚C to prevent pad delamination during localized hand soldering.

Stackup & Impedance Control

Relying on the fabricator’s internal “standard” stackup for high-speed designs is not recommended. The exact layer buildup must be explicitly defined to control crosstalk, radiated emissions, and signal return paths.

1. Impedance Models: Clear impedance requirements must be embedded directly into the mechanical fabrication drawing or the ODB++ metadata.
   • Single Ended: 50Ω ± 10% (Typical standard)
   • Differential Pair: 90Ω or 100Ω ± 10% (Mandatory for USB, PCIe, Ethernet)
2. Copper Balance: Maintain a symmetrical copper distribution around the center of the stackup. Uneven copper weights (e.g., pouring 1 oz on L1 but 0.5 oz on L4) can cause “potato chip” warping during reflow, which leads directly to SMT placement failures.
3. Core vs. Prepreg Construction: The exact glass weave should be defined.
   • For high-speed signals that cross wide gaps in the fiberglass weave, specify the use of low-Dk spread glass styles (e.g., 1067, 1078) to minimize fiber weave effect skew.

Critical Factor

Avoid specifying rigid manufacturer laminate brands (e.g., “Must use Isola 370HR”) unless it is chemically critical. Instead, specify the exact IPC-4101 slash sheet (e.g., “/126”) and the required performance parameters. This allows the fabricator to utilize equivalent verified stock dynamically without triggering a timeline-delaying Engineering Query (EQ).

Via Architecture & Aspect Ratios

Via reliability is a function of plating bath fluid dynamics and the via Aspect Ratio (Board Thickness ÷ Drill Diameter). Exceeding standard aspect ratios prevents adequate plating solution flow, resulting in thin copper knees and eventual open circuits during thermal expansion.

The Geometric Constraints:

• Standard Through-Hole Vias: Limit the Aspect Ratio to 10:1 (e.g., an industry-standard 1.6 mm thick board requires a ≥ 0.16 mm drill bit).
• Microvias (Blind): Limit the Aspect Ratio to 0.8:1. Stacked microvias pose a significant reliability risk; Staggered microvias should be utilized wherever possible to reduce stress concentration at the layer interface.
• Plating Thickness: Require IPC Class 2 average (20 µm) or Class 3 average (25 µm) internal copper plating thickness on the Fab Drawing.

Validation & Evidence

You should require physical evidence from the fabrication house for every production lot to guarantee quality.

1. Impedance Coupons (The TDR Check):

The fabricator must add test coupons to the sacrificial panel waste rail.

• Action: Require an official TDR (Time Domain Reflectometry) report that explicitly matches the coupons to your specific batch serial number.

2. Microsections (Cross-Sections):

• Action: Request the physical acrylic puck or a high-resolution digital image of the microsection.
• Inspect: Carefully check for a pink ring (indicating chemical delamination), wicking (copper migrating along glass fibers), and verify the actual measured plating thickness exactly at the hole knee.

3. Solderability Testing:

• Action: Ensure the surface finish (ENIG, OSP, HASL) passes physical wetting balance tests to prevent “Black Pad” oxidation or non-wetting issues during SMT assembly.

---

Recap: Material Science, Stackups and Via Architecture

Parameter	Requirement	Verification	Action
Laminate Material	Tg ≥ 170°C (Lead-Free Process) Td ≥ 340°C (Rework) Anti-CAF (High-Humidity/Voltage) Z-axis CTE ≤ 3.0% (50-260°C)	IPC-4101 Slash Sheet (e.g., /126)	Specify performance parameters, not brand.
Impedance Control	50Ω ±10% (Single-Ended) 90Ω or 100Ω ±10% (Differential Pairs)	TDR Report on Batch-Specific Coupons	Embed requirements in Fab Drawing/ODB++.
Via Geometry	Aspect Ratio ≤ 10:1 (Through-Hole) Aspect Ratio ≤ 0.8:1 (Blind Microvia) Prefer Staggered over Stacked Microvias	Microsection Analysis	Limit drill size per board thickness.
Plating Quality	Avg. Copper Thickness ≥ 20µm (Class 2) Avg. Copper Thickness ≥ 25µm (Class 3)	Microsection (Check Knee, Wicking, Pink Ring)	Require report per production lot.
Stackup & Balance	Symmetrical Copper Distribution Define Glass Weave (e.g., 1067, 1078)	Warpage Control / Fab Drawing	Prevent “potato chip” warping.