4.1 SPI Recap & Cₚ/Cₚₖ

Solder Paste Inspection (SPI) elevates the process from manual stencil printing to a predictive, data-driven system. By measuring the three-dimensional geometry of each paste deposit—its volume, height, and area—SPI provides an early indicator for potential downstream reflow defects. Translating this raw measurement data into Process Capability Metrics (Cₚ and Cₚₖ) is essential for maintaining a stable, high-yield manufacturing process and managing the Cost of Quality.

SPI Metrics and Defect Prediction

SPI evaluates the printed paste volume against the theoretical volume defined by the stencil aperture. Several key metrics are monitored to anticipate structural issues before the board enters the reflow oven.

SPI Metric	Definition	Defect Signal	Upstream Process Check
Volume (% of Target)	The measured volume of the paste.	Low: Opens, Tombstones, Head-in-Pillow (HIP) risk. High: Bridging.	Stencil Thickness, Aperture Area.
Height (µm)	The peak elevation of the deposit.	Low: Scooping, Paste-on-Mask. High: Excessive pressure forcing paste under the stencil.	Squeegee Pressure, Board Support.
Area (% of Pad)	The physical footprint of the deposit.	High: Bridging, Smear, Solder Balls.	Separation Speed, Paste Rheology.
Transfer Efficiency (TE)	Measured Volume divided by Theoretical Volume.	A general indicator of stencil release quality.	Paste Age, Nano-Coating.

Cost of Error

The fundamental goal of SPI is to predict downstream reflow defects based on upstream print defects. For instance, low Volume TE on passive chips is a primary precursor for tombstoning. Catching it here prevents costly rework later.

Capability Analysis: Cₚ vs. Cₚₖ

Process Capability Indices quantify how well a stable process can meet a given set of engineering tolerance limits. It is important to perform this analysis by feature family, such as 0402 chips or 0.5 mm BGA pads, because each component type has different tolerance requirements.

A) Process Potential (Cₚ)

Cₚ measures the maximum potential capability of the process. It assumes the output is perfectly centered between the Upper Specification Limit (USL) and Lower Specification Limit (LSL). It essentially reflects the width of the data distribution (σ).

Cₚ = ( USL - LSL ) / 6σ

B) Process Performance (Cₚₖ)

Cₚₖ measures the actual performance of the line. It factors in whether the process output mean (µ) is actually centered within the specification limits. If the average print volume is too high or too low, the Cₚₖ will drop, even if the Cₚ (the process width) looks acceptable.

Cₚₖ = min ( ( USL - µ ) / 3σ , ( µ - LSL ) / 3σ )

Cₚₖ Value	Status	Action Required
≥ 1.67	Excellent (Six Sigma)	Maintain control; allocate engineering resources elsewhere.
≥ 1.33	Capable (Minimum Target)	Maintain control; the process is sufficiently stable.
1.00 – 1.33	Marginal	Focus is required to center the mean (µ) or reduce variation (σ).
< 1.00	Not Capable	Defects are likely. The line must be paused to evaluate the process or tooling.

SPI Limits and Capability Targets

It is important to set limits tight enough to accurately predict defects, but wide enough to be achievable on the production floor. For volume on high-risk features, the process should target a Cₚₖ ≥ 1.33.

Feature Family	Recommended TE Specification (USL/LSL)	Primary Cₚₖ Focus
BGA/CSP Pads	90% – 110%	Volume Cₚₖ is critical for collapse symmetry (mitigating Head-in-Pillow (HIP) defects).
Fine-Pitch Gull-Wing	85% – 115%	Area Cₚₖ helps prevent solder bridges.
General Chips (0402)	75% – 125%	Height/Volume Cₚₖ helps prevent tombstoning.
QFN Thermal Pad (Total)	50% – 65% Coverage	Volume Cₚₖ is critical to control solder voiding.

Closed-Loop Feedback and Continuous Improvement

The true value of investing in SPI is utilizing the Cₚₖ trend to drive permanent process improvement.

1. Baseline and Audit: The First Article build establishes the initial Cₚₖ baseline. This baseline verifies the capability of the specific combination of solder paste, stencil, and printer recipe.
2. Center the Mean (µ): If Cₚₖ is low due to poor centering—for example, if µ = 90% when the target is 100%—the primary corrective action is to adjust the squeegee pressure or speed to bring the mean back into the target range.
3. Reduce Variation (σ): If Cₚ is low, the process distribution is too wide. Underlying stability must be improved by adjusting the stencil cleaning cadence, ensuring solder paste hygiene, or considering a higher-quality electroformed stencil.
4. Design Feedback: When a single aperture geometry, like a specific QFN pad, consistently prevents the process from achieving a Cₚₖ ≥ 1.33, the issue often stems from the stencil design. This high-variance data should be shared with the design team so they can revise the aperture shape for the next stencil iteration.

---

Recap: Solder Paste Inspection (SPI) Process Capability

Feature Family	Parameter	Specification Limits (USL/LSL)	Minimum Cₚₖ	Action if Cₚₖ < 1.33
BGA/CSP Pads	Volume (Transfer Efficiency)	90% – 110%	≥ 1.33	Center mean (µ) or reduce variation (σ); focus on collapse symmetry.
Fine-Pitch Gull-Wing	Area (% of Pad)	85% – 115%	≥ 1.33	Center mean (µ) or reduce variation (σ); focus on bridging prevention.
General Chips (e.g., 0402)	Volume/Height (Transfer Efficiency)	75% – 125%	≥ 1.33	Center mean (µ) or reduce variation (σ); focus on tombstoning prevention.
QFN Thermal Pad	Total Volume Coverage	50% – 65%	≥ 1.33	Center mean (µ) or reduce variation (σ); focus on voiding control.
Process Status	Cₚₖ Value	Requirement	—	Required Action
Excellent	≥ 1.67	Maintain control.	—	Allocate resources elsewhere.
Capable	≥ 1.33	Minimum target for stable process.	—	Maintain control.
Marginal	1.00 – 1.33	Process focus required.	—	Center mean (µ) or reduce variation (σ).
Not Capable	< 1.00	Defects likely.	—	Pause line for process/tooling evaluation.