4.1 SPI Recap & Cp/Cpk

Solder pastePaste Inspection (SPI) transforms the stencil printing is the first real gatekeeper of assembly quality, and SPI turns that step into measurable, actionable data. By linking paste volume, height, and area to known downstream failure modes, manufacturers can predict defects before they ever appear at AOI, AXI, or test. Capability analysis adds another layer of insight, showing not just whether prints are in spec, but whether the process itself is stable and centered enough to stay there. With well-chosen limits, dashboards, and disciplined habits, SPI evolves from ana inspectionmanual toolart into a predictive, data-driven system. By measuring the three-dimensional geometry of every paste deposit — Volume, Height, and Area — SPI provides the earliest warning sign for downstream reflow defects (Chapter 3.5). The translation of this raw measurement data into Process Capability Metrics (C_p and C_pk) is essential for achieving a stable, high-yield manufacturing process control engine that drivesminimizes yieldthe andCost predictability.of Quality (CoQ).

4.1.1 Why SPI isMetrics and Defect Prediction

SPI measures the best early-warning system

SPI (solderprinted paste inspection)volume measuresagainst the theoretical volume defined by the stencil aperture (Chapter 1.4).

SPI Metric	Definition	Defect Signal	Upstream Process Check
Volume (% of Target)	The measured mass of paste.	Low: Opens, Tombstones, HIP risk. how muchHigh: pasteBridging.	Stencil landedThickness (volume)Chapter 1.3), howAperture tallArea it(Chapter is1.4).
Height (µm)	The peak elevation of the deposit.	heightLow:), andScooping, Paste-on-Mask. how wideHigh: itExcessive spreadpressure forcing paste under stencil.	Squeegee Pressure (area)—padChapter by pad. Because nearly every reflow defect starts with too little1.5), tooBoard muchSupport.
Area (% of Pad)	The footprint of the deposit.	High: Bridging, Smear, Solder Balls.	Separation Speed (Chapter 1.5), or misplacedPaste Rheology paste,(Chapter clean SPI data lets you stop escapes before AOI/AXI/Test ever see them.1.2).
Transfer Efficiency (TE)	Measured =Volume / Theoretical Volume.(measured	The volumeoverall ÷indicator theoreticalof volume)stencil ×release 100%quality.	Paste Age (TheoreticalChapter volume1.2), =Nano-Coating aperture(Chapter area × stencil thickness.)1.3).

Process Note:Think The goal of SPI asis yourto “predict a reflow defect (Chapter 3.5) based on a print health”abnormality dashboard;(Chapter Cp/Cpk1.5). thenFor tellexample, youlow whetherVolume thatTE healthon passive chips is the primary precursor to the capableTombstoning defect.

4.1.2 Capability Analysis: C_p vs. C_pk

Process Capability Indices quantify how well a stable process can meet a set of engineering tolerance limits. This analysis must be performed by feature family (e.g., 0402 chips, 0.5 mm BGA pads) because each has different tolerance requirements.

A) Process Potential (C_p )

C_p measures the maximum potential capability of the process, assuming the output is perfectly centered between the Upper Specification Limit (USL) and Lower Specification Limit (LSL). It only reflects the width of stayingthe insidedistribution your(σ).

spec

C_p = ( USL - LSL ) / 6σ

B) Process Performance (C_pk)

C_pk measures the actual performance by factoring in whether the process output (µ, the mean) is centered within the specification limits. If the average print volume is too high or too low, the C_pk drops, even whenif the lineC_p wiggles.(process width) is acceptable.

C_pk

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=

4.1.2 Map SPI signals to real defectsmin (cause →( effect)

USL - µ ) / 3σ , ( µ - LSL ) / 3σ )

SPICpk​ patternValue	Usual outcome downstreamStatus	FirstAction place you’ll feel itRequired
Low≥ volume (TE↓) on chip pads1.67	Opens,World tombstones,Class skew(Six Sigma)	AOIMaintain; afterfocus reflowresources elsewhere.
High≥ volume (TE↑) / area creep on fine pitch1.33	BridgingCapable (Minimum Target)	AOIMaintain +control; ICTprocess shortsis stable.
Low1.00 total– volume on QFN thermal1.33	Voids, weak thermal pathMarginal/Warning	AXIImmediate +focus thermalrequired testto center the mean (µ) or reduce variation (σ).
Uneven< TE across BGA field1.00	HIPNot risk (balls don’t collapse evenly)	AXI (collapse), FCT (intermittents)
High area beyond pad	Solder balls/smearCapable	AOIDefects cosmeticsare guaranteed. Stop the line and change the process/tooling.

If you keep TE inside sane bands (from Chapter 7.6) and area/height stable, most of the reflow Pareto simply… doesn’t happen.

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4.1.3 SPI Limits and Capability 101 (what Cp/Cpk actually say)Targets

• Cp

  Limits checksmust thebe set tight enough to predict defects but wide enough to be achievable. The process should target widthC of your process vs the width_{pk of your spec window:}
   Cp = (USL − LSL) ÷ (6σ)
   (USL/LSL are your TE limits for that feature family; σ is the TE standard deviation.)

• Cpk adds centering:
   Cpk = min((USL − μ) ÷ (3σ), (μ − LSL) ÷ (3σ))
   (μ is the mean TE. If you’re off-center, Cpk drops.)

Rules of thumb for SPI:

• Cpk ≥ 1.33 →for comfyvolume (stable,on centeredall prints).
• 1.00–1.33high-risk → watch list (tighten cleaning/recipe).
• < 1.00 → not capable (expect defects unless you change the process).

Always compute by feature family (chips vs QFN edges vs BGA pads vs thermal pads). Mixing families hides trouble.

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4.1.4 Setting sensible SPI limits (specs you can live with)

Start with Chapter 7.6’s defaults, then tighten per product:features.

Feature Family	SuggestedRecommended TE specSpecification (USL/LSL)	WhyPrimary Cpk​ Focus
ChipsBGA/CSP 0201–0603Pads	75%90% –125% 110%	Volume CpkBalances tombstonesis vscritical bridgesfor collapse symmetry (HIP mitigation).
Fine-pitchPitch gull-wingGull-Wing	85% – 115%	Area CpkTighter tois preventcritical bridgesfor bridging prevention.
QFN/DFNGeneral edgeChips pads(0402)	75% – 125%	85%–115%Height/Volume C	pkKeep edgesis wetcritical withoutfor overflowtombstoning prevention.
QFN thermalThermal Pad (total)Total)	50% – 65% coverageCoverage	Volume CpkAvoid float;is controlcritical voidsfor void control.

4.1.4 Closed-Loop Feedback and Continuous Improvement

The true value of SPI is not the inspection itself, but the use of the C_pk trend to drive permanent improvement.

1. Baseline and Audit: The First Article (FA) (Chapter 2.5) must establish the initial C_pk baseline. This baseline proves the capability of the specific paste, stencil, and recipe combination.
2. Center the Mean (µ): If C_pk is low due to poor centering (e.g., µ = 90% when the target is 100%), the primary action is to adjust the squeegee pressure or speed (Chapter 1.5) to bring the mean into the target range.
3. Reduce Variation (σ): If C_p is low, the process is too wide. The action is to improve fundamental stability via stencil cleaning cadence (Chapter 1.5), paste hygiene (Chapter 1.2), or switching to a higher-quality Electroformed stencil (Chapter 1.3).
4. Design Feedback: When a single aperture geometry (e.g., a specific QFN pad) consistently prevents the process from achieving C_pk ≥ 1.33, the failure lies in the Stencil Design (Chapter 1.4). The high σ data must be fed back to the design team to revise the aperture shape for the next stencil iteration.

Final Checklist: Capability Control

Item	Status	Action/Metric
Capability	Cpk achieved for Volume ≥ 1.33 for all high-risk features.	Dashboard Tracking of Cpk by family.
BGAProcess pads	90%–110%Centering	CollapsePrint symmetryMean for(µ) HIPis controlwithin ±5% of the target.	Adjust Squeegee Parameters (Chapter 1.5).
Process Width	Cp is high (≥ 1.33).	Ensure Feeder/Paste Hygiene and minimize print variation (σ).
Golden Limits	SPI limits are Feature-Specific and locked in the Golden Recipe.	Prevents high-risk features from being run with loose tolerances.

Pair TE specs with height floors (e.g., ≥60–70% of stencil thickness) to catch “paste on mask.”

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4.1.5 A tiny worked example (numbers that talk)

Feature: 0402 chips
 Spec: TE 75–125% (LSL=75, USL=125)
 Pilot data (1000 pads): μ = 96%, σ = 6%

1. Cp
    USL − LSL = 125 − 75 = 50
    6σ = 6 × 6 = 36
    Cp = 50 ÷ 36 = 1.39 (capable width)
   
2. Cpk
    USL − μ = 125 − 96 = 29 → 29 ÷ (3×6=18) = 1.61
    μ − LSL = 96 − 75 = 21 → 21 ÷ 18 = 1.17
    Cpk = min(1.61, 1.17) = 1.17 (a bit off-center low)
   

Read it: your prints are tight, but biased low. Expect tombstone risk under stress. Fix by nudging blade pressure/speed or aperture reduction (if over-reduced), then recheck.

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4.1.6 How to use capability (not just calculate it)

1. Baseline per family on the FA lot (+ first real lot).
2. Center first (shift μ toward target), then tighten spread (reduce σ) via:
3. • Printer recipe: angle/pressure/speed, separation, cleaning cadence.
   • Stencil tweaks: nano-coating, step maps, aperture edits (7.3–7.4).
   • Paste hygiene: bead size, open time, fresh jar policy (7.2).
3. Promote families with Cpk ≥1.33 to “green”; focus ops/engineering on the orange/red families.
   

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4.1.7 Dashboards that prevent defects (what to plot)

• TE Cpk by family (chips, QFN edge, QFN thermal total, BGA pads).
• First-Print Pass % and Wipes/Board (printer stability).
• Reprint rate (local recovery doing work?)
• Bridging/Tombstone hits at AOI overlaid on SPI heat-maps for the same panels.
• Before/after markers when you change stencil or recipe.

If AOI calls drop where Cpk rose, you’ve proven cause→effect.

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4.1.8 Small habits that make stats trustworthy

• Use I-MR charts per family; ignore the very first panel after a wipe when setting control limits.
• Keep SPI illumination profiles per mask color/finish; bad lighting fakes area/height drift.
• Run a weekly GR&R on a golden board (3 ops × 3 repeats) so σ is real, not a metrology artifact.
• Don’t average families together; worst family sets your risk.
  

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4.1.9 Pocket checklist (print-side)

• TE USL/LSL set per family; height floors enabled
• Cp/Cpk computed on FA + first lot; orange/red families identified
• Actions assigned: center μ (recipe/aperture), shrink σ (cleaning/foil/paste)
• SPI ↔ AOI overlay reviewed after changes; defect Pareto moved the right way
• Golden limits/recipes updated if the fix sticks
  

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When SPI data is translated into capability metrics, tied to family-specific limits, and acted on with recipe or stencil adjustments, the factory moves from chasing defects to preventing them. The reward is higher first-pass yield, fewer surprises at reflow, and a smoother, more controlled production line.