4.1 SPI Recap & Cp/Cpk

Solder Paste Inspection (SPI) transforms the stencil printing process from a manual art into a predictive, data-driven system. By measuring the three-dimensional geometry of every paste deposit — Volume, Height, and Area — SPI provides the earliest warning sign for downstream reflow defects (Chapter 3.5). The translation of this raw measurement data into Process Capability Metrics (C_p and C_pk) is essential for achieving a stable, high-yield manufacturing process that minimizes the Cost of Quality (CoQ).

4.1.1 SPI Metrics and Defect Prediction

SPI measures the printed paste volume against the theoretical volume defined by the stencil aperture (Chapter 1.4).

SPI Metric	Definition	Defect Signal	Upstream Process Check
Volume (% of Target)	The measured mass of paste.	Low: Opens, Tombstones, HIP risk. High: Bridging.	Stencil Thickness (Chapter 1.3), Aperture Area (Chapter 1.4).
Height (µm)	The peak elevation of the deposit.	Low: Scooping, Paste-on-Mask. High: Excessive pressure forcing paste under stencil.	Squeegee Pressure (Chapter 1.5), Board Support.
Area (% of Pad)	The footprint of the deposit.	High: Bridging, Smear, Solder Balls.	Separation Speed (Chapter 1.5), Paste Rheology (Chapter 1.2).
Transfer Efficiency (TE)	Measured Volume / Theoretical Volume.	The overall indicator of stencil release quality.	Paste Age (Chapter 1.2), Nano-Coating (Chapter 1.3).

Process Note: The goal of SPI is to predict a reflow defect (Chapter 3.5) based on a print abnormality (Chapter 1.5). For example, low Volume TE on passive chips is the primary precursor to the Tombstoning defect.

4.1.2 Capability Analysis: C_p vs. C_pk

Process Capability Indices quantify how well a stable process can meet a set of engineering tolerance limits. This analysis must be performed by feature family (e.g., 0402 chips, 0.5 mm BGA pads) because each has different tolerance requirements.

A) Process Potential (C_p )

C_p measures the maximum potential capability of the process, assuming the output is perfectly centered between the Upper Specification Limit (USL) and Lower Specification Limit (LSL). It only reflects the width of the distribution (σ).

C_p = ( USL - LSL ) / 6σ

B) Process Performance (C_pk)

C_pk measures the actual performance by factoring in whether the process output (µ, the mean) is centered within the specification limits. If the average print volume is too high or too low, the C_pk drops, even if the C_p (process width) is acceptable.

C_pk = min ( ( USL - µ ) / 3σ , ( µ - LSL ) / 3σ )

Cpk​Cpk​ Value	Status	Action Required
≥ 1.67	World Class (Six Sigma)	Maintain; focus resources elsewhere.
≥ 1.33	Capable (Minimum Target)	Maintain control; process is stable.
1.00 – 1.33	Marginal/Warning	Immediate focus required to center the mean (µ) or reduce variation (σ).
< 1.00	Not Capable	Defects are guaranteed. Stop the line and change the process/tooling.

4.1.3 SPI Limits and Capability Targets

Limits must be set tight enough to predict defects but wide enough to be achievable. The process should target C_pk ≥ 1.33 for volume on all high-risk features.

Feature Family	Recommended TE Specification (USL/LSL)	Primary Cpk​ Focus
BGA/CSP Pads	90% – 110%	Volume Cpk is critical for collapse symmetry (HIP mitigation).
Fine-Pitch Gull-Wing	85% – 115%	Area Cpk is critical for bridging prevention.
General Chips (0402)	75% – 125%	Height/Volume Cpk is critical for tombstoning prevention.
QFN Thermal Pad (Total)	50% – 65% Coverage	Volume Cpk is critical for void control.

4.1.4 Closed-Loop Feedback and Continuous Improvement

The true value of SPI is not the inspection itself, but the use of the C_pk trend to drive permanent improvement.

1. Baseline and Audit: The First Article (FA) (Chapter 2.5) must establish the initial C_pk baseline. This baseline proves the capability of the specific paste, stencil, and recipe combination.
2. Center the Mean (µ): If C_pk is low due to poor centering (e.g., µ = 90% when the target is 100%), the primary action is to adjust the squeegee pressure or speed (Chapter 1.5) to bring the mean into the target range.
3. Reduce Variation (σ): If C_p is low, the process is too wide. The action is to improve fundamental stability via stencil cleaning cadence (Chapter 1.5), paste hygiene (Chapter 1.2), or switching to a higher-quality Electroformed stencil (Chapter 1.3).
4. Design Feedback: When a single aperture geometry (e.g., a specific QFN pad) consistently prevents the process from achieving C_pk ≥ 1.33, the failure lies in the Stencil Design (Chapter 1.4). The high σ data must be fed back to the design team to revise the aperture shape for the next stencil iteration.

Final Checklist: Capability Control

Item	Status	Action/Metric
Capability	Cpk achieved for Volume ≥ 1.33 for all high-risk features.	Dashboard Tracking of Cpk by family.
Process Centering	Print Mean (µ) is within ±5% of the target.	Adjust Squeegee Parameters (Chapter 1.5).
Process Width	Cp is high (≥ 1.33).	Ensure Feeder/Paste Hygiene and minimize print variation (σ).
Golden Limits	SPI limits are Feature-Specific and locked in the Golden Recipe.	Prevents high-risk features from being run with loose tolerances.