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4.1 SPI Recap & Cp/Cpk

Solder paste printing is the first real gatekeeper of assembly quality, and SPI turns that step into measurable, actionable data. By linking paste volume, height, and area to known downstream failure modes, manufacturers can predict defects before they ever appear at AOI, AXI, or test. Capability analysis adds another layer of insight, showing not just whether prints are in spec, but whether the process itself is stable and centered enough to stay there. With well-chosen limits, dashboards, and disciplined habits, SPI evolves from an inspection tool into a process control engine that drives yield and predictability.

4.1.1 Why SPI is the best early-warning system

SPI (solder paste inspection) measures how much paste landed (volume), how tall it is (height), and how wide it spread (area)—pad by pad. Because nearly every reflow defect starts with too little, too much, or misplaced paste, clean SPI data lets you stop escapes before AOI/AXI/Test ever see them.

  • Transfer Efficiency (TE) = (measured volume ÷ theoretical volume) × 100%
    (Theoretical volume = aperture area × stencil thickness.)

Think of SPI as your “print health” dashboard; Cp/Cpk then tell you whether that health is capable of staying inside your spec even when the line wiggles.



4.1.2 Map SPI signals to real defects (cause → effect)

SPI pattern

Usual outcome downstream

First place you’ll feel it

Low volume (TE↓) on chip pads

Opens, tombstones, skew

AOI after reflow

High volume (TE↑) / area creep on fine pitch

Bridging

AOI + ICT shorts

Low total volume on QFN thermal

Voids, weak thermal path

AXI + thermal test

Uneven TE across BGA field

HIP risk (balls don’t collapse evenly)

AXI (collapse), FCT (intermittents)

High area beyond pad

Solder balls/smear

AOI cosmetics

If you keep TE inside sane bands (from Chapter 7.6) and area/height stable, most of the reflow Pareto simply… doesn’t happen.



4.1.3 Capability 101 (what Cp/Cpk actually say)

  • Cp checks the width of your process vs the width of your spec window:
    Cp = (USL − LSL) ÷ (6σ)
    (USL/LSL are your TE limits for that feature family; σ is the TE standard deviation.)
  • Cpk adds centering:
    Cpk = min((USL − μ) ÷ (3σ), (μ − LSL) ÷ (3σ))
    (μ is the mean TE. If you’re off-center, Cpk drops.)

Rules of thumb for SPI:

  • Cpk ≥ 1.33 → comfy (stable, centered prints).
  • 1.00–1.33 → watch list (tighten cleaning/recipe).
  • < 1.00 → not capable (expect defects unless you change the process).

Always compute by feature family (chips vs QFN edges vs BGA pads vs thermal pads). Mixing families hides trouble.



4.1.4 Setting sensible SPI limits (specs you can live with)

Start with Chapter 7.6’s defaults, then tighten per product:

Family

Suggested TE spec (USL/LSL)

Why

Chips 0201–0603

75%–125%

Balances tombstones vs bridges

Fine-pitch gull-wing

85%–115%

Tighter to prevent bridges

QFN/DFN edge pads

85%–115%

Keep edges wet without overflow

QFN thermal (total)

50%–65% coverage

Avoid float; control voids

BGA pads

90%–110%

Collapse symmetry for HIP control

Pair TE specs with height floors (e.g., ≥60–70% of stencil thickness) to catch “paste on mask.”



4.1.5 A tiny worked example (numbers that talk)

Feature: 0402 chips
Spec: TE 75–125% (LSL=75, USL=125)
Pilot data (1000 pads): μ = 96%, σ = 6%

  1. Cp
    USL − LSL = 125 − 75 = 50
    6σ = 6 × 6 = 36
    Cp = 50 ÷ 36 = 1.39 (capable width)
  2. Cpk
    USL − μ = 125 − 96 = 29 → 29 ÷ (3×6=18) = 1.61
    μ − LSL = 96 − 75 = 21 → 21 ÷ 18 = 1.17
    Cpk = min(1.61, 1.17) = 1.17 (a bit off-center low)

Read it: your prints are tight, but biased low. Expect tombstone risk under stress. Fix by nudging blade pressure/speed or aperture reduction (if over-reduced), then recheck.



4.1.6 How to use capability (not just calculate it)

  1. Baseline per family on the FA lot (+ first real lot).
  2. Center first (shift μ toward target), then tighten spread (reduce σ) via:
    • Printer recipe: angle/pressure/speed, separation, cleaning cadence.
    • Stencil tweaks: nano-coating, step maps, aperture edits (7.3–7.4).
    • Paste hygiene: bead size, open time, fresh jar policy (7.2).
  4. Promote families with Cpk ≥1.33 to “green”; focus ops/engineering on the orange/red families.



4.1.7 Dashboards that prevent defects (what to plot)

  • TE Cpk by family (chips, QFN edge, QFN thermal total, BGA pads).
  • First-Print Pass % and Wipes/Board (printer stability).
  • Reprint rate (local recovery doing work?)
  • Bridging/Tombstone hits at AOI overlaid on SPI heat-maps for the same panels.
  • Before/after markers when you change stencil or recipe.

If AOI calls drop where Cpk rose, you’ve proven cause→effect.



4.1.8 Small habits that make stats trustworthy

  • Use I-MR charts per family; ignore the very first panel after a wipe when setting control limits.
  • Keep SPI illumination profiles per mask color/finish; bad lighting fakes area/height drift.
  • Run a weekly GR&R on a golden board (3 ops × 3 repeats) so σ is real, not a metrology artifact.
  • Don’t average families together; worst family sets your risk.



4.1.9 Pocket checklist (print-side)

  • TE USL/LSL set per family; height floors enabled
  • Cp/Cpk computed on FA + first lot; orange/red families identified
  • Actions assigned: center μ (recipe/aperture), shrink σ (cleaning/foil/paste)
  • SPI ↔ AOI overlay reviewed after changes; defect Pareto moved the right way
  • Golden limits/recipes updated if the fix sticks



When SPI data is translated into capability metrics, tied to family-specific limits, and acted on with recipe or stencil adjustments, the factory moves from chasing defects to preventing them. The reward is higher first-pass yield, fewer surprises at reflow, and a smoother, more controlled production line.


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