5.1 Strategy & Coverage

AElectrical test is not an option; it is a financial and technical firewall. The goal of a well-designed test strategy is to achieve the backbonerequired Defect Coverage (ensuring product quality) at the minimum Cost of reliableTest electronics(CoT) manufacturing,(protecting balancing cost, speed,throughput and coverageprofit). acrossThis requires strategically deploying a product’smix lifecycle.of Structuraltools—from high-speed structural checks like (ICT, flyingFlying probe,Probe, andBSCAN) BSCANto provide the cheapest certainty by filtering out common build defects beforein-depth functional testingverification ever begins. Functional and system-level tests then focus on what truly matters to the end user, ensuring confidence without overloading the line.(FCT). The artmost lieseffective instrategy choosing the right mix for product type, volume, and risk, so quality targets are met without turning throughput into the bottleneck

5.1.1 The problem in plain words

You can test forever and still miss things—or test almost nothing and ship pain. The trick is to catchcatches the common, costlycheap-to-fix structural faults early (cheap, fast stations) and leavereserves onlythe aslower, more expensive functional checks for customer-critical behaviors.

5.1.1 The Test Strategy Imperative

You can't test every node on every net forever. The most efficient strategy follows the principle: small,Catch meaningfulthe cheapest faults first. setStructural of risks to later, slower tests. We’ll build a mix that hits your defect-per-million (DPPM) and uptime targets without turning the line into a parking lot.

Think in three layers:

• Structural: “Is it built right?”defects (opens, shorts, wrong value/orientation)parts) are common and cheap to fix early in the line. Functional defects (timing, integration) are complex, expensive, and should be the last thing you check.

  Three Layers of Fault Coverage

  Effective testing requires a layered approach to fault detection:

  1. Structural: "Is it built right?" Verifies connectivity (opens/shorts), component presence, and component values (passive checks). Best Detector: ICT/Flying Probe/BSCAN.
  2. Functional (FCT): "Does it work?" Powers the board, initializes circuits, and verifies basic hardware blocks (e.g., memory, power rails, basic communication loops).
  3. FunctionalSystem/Application:: “Does it behave?” (power-up, comms, timing, load).
  3. System: “"Does it do what the jobcustomer in context?” (firmware + peripherals + use-case).

Catch structural faults beforeneeds?" youRuns wastefinal timefirmware, ontests functionalinterfaces ones.(Ethernet, USB), and validates end-use cases.

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5.1.2 YourThe testTest toolbeltToolbelt: Cost and Coverage

Choosing the right tool depends on your production volume (whatamortization) eachand isboard gooddensity at)(access).

Tool	What itIt actuallyChecks does	Coverage sweet spot(Coverage)	Cost & cycleCycle feelTime	When to reachUse for itIt
ICT (In-Circuit Test)	NailsHigh opens/shortsStructural Coverage., wrongOpens, shorts, resistor/capacitor values, orientation;orientation, powers-onpassive safely and does quick analog checks	High structural coverage on accessible nets; great at passives, nets, power railsverification.	High NRE (fixture)Fixture Cost), veryVery fastFast per board(Seconds).	High volumeHigh-Volume, goodproduction probewhere accessfixture cost amortizes quickly (bed-of-nails)> 30k units).
Flying Probe (FPT/MDA)	Structural Coverage.ICT withoutSame aas fixture;ICT, but probes move	Broad structural on low/med volume; ECO-friendlydynamically.	Low NRE (No Fixture), slowerSlower cycle(Minutes).	NPI,NPI low(New volume,Product Intro), Low/Mid-Volume, or High-Mix lines with frequent design changes (ECOs).
BSCAN (Boundary Scan/JTAG)	Hidden Net Continuity.Shifts pinsTests digital interconnects under BGAs, tests hidden nets,BGAs/CSPs; programs flash/MCUsFlash/MCUs.	GreatLow under fine-pitch/BGANRE., chainsCycle digitaltime nets	Lowis NRE,very short cycle(parallel testing).	Dense boards, with limited pads,test needpad access; essential for BGA testing and in-line programming.
FCT (Functional Test)	Full Functionality. Powers theup, boardchecks andexternal I/O, runs realfirmware, behaviors	Integrationtests defects,critical interfaces,performance timing(speed, current draw).	Medium NRE (fixture/code)Code & Simple Fixture), medium–slowMedium-to-Slow cyclecycle.	Final confidence; customer-visible features
Boundary “Lite” (Power-on checks)	Smoke test: rails, idle current, clocks	Catastrophic build/polarity faults	Lowest NRE, seconds	Early screen beforegate longto testsconfirm the product meets customer requirements.

Rule of thumb: Structural first, functional last. Let ICT/Flying Probe/BSCAN remove the trash; let FCT prove what matters.

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5.1.3 CoverageStrategic model (aimMix by faultProduct class)Type

FaultThe class	Typicaloptimal root	Besttest detector	Targetroute coverage
Opens/shorts	Solder,is via,a stencil, handling	ICT/Flying Probe/BSCAN	≈ 95–99%cocktail of nets reachable
Wrong value/orientation	Kitting, feeder flips	ICTinspection (value/polarity)Chapter +4) AOIand backup	100%electrical oftest, polarized,tailored ≥95% of value-critical
BGA hidden defects	Paste/reflow/HIP	AXI + BSCAN interconnect	Per-ball void/continuity limits met
Power integrity	Assembly + layout	ICT (rails/IR), FCT smoke	100% critical rails
Interface timing/logic	Design/firmware	FCT (loopbacks, loads)	All customer-facing features exercised

Structural coverage (opens/shorts/polarity/value) isto the cheapestproject's yieldrisk driver. Don’t skimp there.profile.

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5.1.4 Strategy by product type (pick your template)

Product Scenario	Good,Recommended fastTest mixRoute	Why it worksRationale
High-volumeVolume consumerConsumer	SPI → AOI → ICT + BSCAN (bed-of-nails)Program) → Short FCT; BSCAN for BGAs + in-line programming	Fixture cost amortizes;Amortize ICT slamsfixture structuralcost; faults;use BSCAN to move programming off-line; brief FCT checksto confirm basic user features onlyfeatures.
NPI / Mid-volume industrialVolume	SPI → AOI → Flying Probe + BSCAN → Focused FCT	LowMinimize NRE;upfront NRE risk; probe handles ECOs easily; BSCAN coversensures BGAs;BGA probe cycles acceptableintegrity.
Safety-criticalCritical / medicalDense	AOI/SPI → AOI → AXI Sampling → ICT (max coverage) + BSCAN (Max Coverage) → Full FCT + burn-in/soakStress/Burn-In	CompliancePrioritize +coverage risk;(99% paystructural); the time to prove it
Complex, frequently changing NPI	AOI → Flying Probe + AXI/BSCAN →ensure Developerhidden FCTjoints (modular)	Zero/loware fixture;good; changesmandatory don’t break thesoak test linevalidates long-term reliability.

Cost Math (The Manager View)

YouFixture canPayback start(Break-Even NPI on flying probe, then switch to ICT when the rev stabilizes and volume rises.Quantity):

Break-Even

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5.1.5 Cost math you actually use

• Fixture payback (very back-of-napkin):
   Break-even qtyQTY ≈ ICT Fixture NRE ÷Cost / (Probe-station minutesFPT/ICT savedTime ×Difference $/minSaved ofper lineBoard time)
  x Line Cost per Minute)

  If an ICT fixture costs $50k and saves 1 minute per board vsover flying probe and(at your$1.50 burdened/ minutemin line cost), the payback is 33,333 boards.

  5.1.4 Planning and Coverage Mandates

  The test strategy must be defined during the design phase (Design for Testability, DFT).

  1. BSCAN Integration: Designate $2JTAG headers/test points, on the PCB early. Use Boundary Scan (IEEE 1149.1) to test all digital net connectivity under BGAs, effectively turning a $60kdifficult fixturephysical paystest backinto ata ~30kfast, boards.digital one.
  2. CycleCoverage time budgetTarget:: Aim for ≥ 95% Structural Net Coverage (all nets reachable by ICT/Probe/BSCAN). Don't start manufacturing until coverage is quantified and approved.
  3. TAKT Time Budget: The total test time (ICT + BSCAN + FCT) must fitbe yourless than the required TAKT Time (the rate at which products must be produced). If not,test time is the bottleneck, you must split FCT (parallelizeparallel FCT), trim (structural earlier),test) or batch (programming off-line with BSCAN).

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5.1.6 BSCAN planning (earlier than you think)

• Put JTAG headers (or test pads) ontrim the PCA early (see 3.4) and chain key devices (MCU/FPGA/flash).
• Use BSCAN for digital interconnect under BGAs and programming (saves a whole test step).
• Keep the chain short and documented in the Golden Pack; boundary scripts live with test code.

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5.1.7 Building the line route (an example that flows)

1. AOI post-reflow (fast structural cues).
2. AXI sampling (if BGAs/QFN thermals are high risk).
3. ICT / Flying Probe + BSCAN (kill structural faults, program devices).
4. FCT (short, meaningful): power-up, comms, one or two use-case loops with load.
5. Optional stress (soak/burn-in) for harsh-duty products.
6. Pack-out with traceability (Chapter 4).

Each step should fail fast to NG flow; don’t push a sick board into a long test.

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5.1.8 Coverage & SLA targets (write them down)

• Structural net coverage: ≥95% reachable nets tested (ICT/Probe/BSCAN).
• Polarity/value: 100%scope of polarizedthe partsstructural checked; value checks on BOM-critical components.checks.
• AXI: BGA collapse/voids within limit on sample rate N per lot.
• FCT: All customer-visible functions exercised; power & safety guards always.
• Throughput: test stations not the bottleneck; overall First Pass Yield hits plan.
• Field: shipped DPPM and RMA within SLA.

If a target slips, decide whether to add coverage (upstream) or tighten the process (printing/reflow/placement).

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5.1.9Final FastChecklist: decisionTest tableStrategy (print this)Mandates

QuestionRequirement	IfMetric Yes/ Goal	IfAction NoMandate
Structural Coverage	Volume≥ high95% enoughof toall amortizeaccessible fixture?nets tested for opens/shorts.	GoCoverage ICT;report keepgenerated Flyingand Probeapproved forby ECOs	StayQuality FlyingEngineering Probe for now(QE).
LotsHidden ofJoint BGAs / poor access?Test	AddAll BSCAN;BGAs/QFNs plancovered chain/header early	ICT may be enough
TAKT tight?	Move programming toby BSCAN earlier;(for trimdigital FCTnets) to essentials	Keep longer FCT
Safety/field risk high?	Addor AXI sampling +(for stress; raise structural coveragevoids/HIP).	FocusJTAG headers/test points must be placed on costthe & speedPCB.
Test Route Design	ManyRoute ECOschoice expected?(ICT vs. Flying Probe) based on projected volume and NRE payback.	Structural test must precede FCT to avoid wasting time on broken boards.
Throughput Control	Total Test Cycle Time ≤ TAKT Time.	KeepIf bottlenecked, FCT must be split into parallel stations or trimmed to core features.
Final Confidence	FCT must fully exercise all Probecustomer-facing + BSCANfeatures through ramp.	FreezePower/safety revchecks →(like investrail involtage and current draw) run 100% of the time.ICT

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5.1.10 Pocket checklists

At NPI kickoff

• Fault classes ranked (what would really hurt the customer?)
• DFT: pads/headers for ICT/BSCAN planned
• Provisional route chosen (Probe vs ICT; AXI need; FCT scope)

Before release to volume

• Structural coverage ≥ 95% nets (report attached)
• BSCAN scripts + programming times validated
• FCT runs inside time budget; features mapped to requirements
• SLA written: DPPM, RMA, TAKT, sample rates (AXI)

Continuous improvement

• Pareto from AOI/AXI/FCT feeds back to stencil/profile (Ch. 7–9)
• Fixture/sequence changes re-timed; dashboard shows test as non-constraint
• Field returns loop to update coverage where it counts

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In practice, the most efficient strategy catches structural faults early, reserves functional testing for customer-critical behaviors, and evolves coverage based on field data and defect trends. Doing so minimizes wasted time on bad boards, controls cost, and delivers dependable products at scale.