2.22 Strategy & Coverage

Electrical test is not an option; it is a financial and technical firewall. The goal of a well-designed test strategy is to achieve the required Defect Coverage (ensuring product quality) at the minimum Cost of Test (CoT) (protecting throughput and profit). This requires strategically deploying a mix of tools—tools — from high-speed structural checks (ICT, Flying Probe, BSCAN) to in-depth functional verification (FCT). The most effective strategy catches the common, cheap-to-fix structural faults early and reserves the slower, more expensive functional checks for customer-critical behaviors.

5.1.2.22.1 The Test Strategy Imperative

You can't test every node on every net forever. The most efficient strategy follows the principle: Catch the cheapest faults first. Structural defects (opens, shorts, wrong parts) are common and cheap to fix early in the line. Functional defects (timing, integration) are complex, expensive, and should be the last thing you check.

Three Layers of Fault Coverage

Effective testing requires a layered approach to fault detection:

1. Structural: "Is it built right?" Verifies connectivity (opens/shorts), component presence, and component values (passive checks). Best Detector: ICT/Flying Probe/BSCAN.
2. Functional (FCT): "Does it work?" Powers the board, initializes circuits, and verifies basic hardware blocks (e.g., memory, power rails, basic communication loops).
3. System/Application: "Does it do what the customer needs?" Runs final firmware, tests interfaces (Ethernet, USB), and validates end-use cases.

5.1.2.22.2 The Test Toolbelt: Cost and Coverage

Choosing the right tool depends on your production volume (amortization) and board density (access).

Tool	What It Checks (Coverage)	Cost & Cycle Time	When to Use It
ICT (In-Circuit Test)	High Structural Coverage. Opens, shorts, resistor/capacitor values, orientation, passive verification.	High NRE (Fixture Cost), Very Fast (Seconds).	High-Volume production where fixture cost amortizes quickly (> 30k units).
Flying Probe (FPT/MDA)	Structural Coverage. Same as ICT, but probes move dynamically.	Low NRE (No Fixture), Slower (Minutes).	NPI (New Product Intro), Low/Mid-Volume, or High-Mix lines with frequent design changes (ECOs).
BSCAN (Boundary Scan/JTAG)	Hidden Net Continuity. Tests digital interconnects under BGAs/CSPs; programs Flash/MCUs.	Low NRE. Cycle time is very short (parallel testing).	Dense boards with limited test pad access; essential for BGA testing and in-line programming.
FCT (Functional Test)	Full Functionality. Powers up, checks external I/O, runs firmware, tests critical performance (speed, current draw).	Medium NRE (Code & Simple Fixture), Medium-to-Slow cycle.	Final gate to confirm the product meets customer requirements.

5.1.2.22.3 Strategic Mix by Product Type

The optimal test route is a cocktail of inspection (Chapter 4) and electrical test, tailored to the project's risk profile.

Product Scenario	Recommended Test Route	Rationale
High-Volume Consumer	SPI → AOI → ICT + BSCAN (Program) → Short FCT	Amortize ICT fixture cost; use BSCAN to move programming off-line; brief FCT to confirm basic user features.
NPI / Mid-Volume	SPI → AOI → Flying Probe + BSCAN → Focused FCT	Minimize upfront NRE risk; probe handles ECOs easily; BSCAN ensures BGA integrity.
Safety-Critical / Dense	SPI → AOI → AXI Sampling → ICT + BSCAN (Max Coverage) → Full FCT + Stress/Burn-In	Prioritize coverage (99% structural); AXI/BSCAN ensure hidden joints are good; mandatory soak test validates long-term reliability.

Cost Math (The Manager View)

Fixture Payback (Break-Even Quantity):

Break-Even QTY ≈ ICT Fixture NRE Cost / ( FPT/ICT Time Difference Saved per Board x Line Cost per Minute)

If an ICT fixture costs $50k and saves 1 minute per board over flying probe (at $1.50 / min line cost), the payback is 33,333 boards.

5.1.2.22.4 Planning and Coverage Mandates

The test strategy must be defined during the design phase (Design for Testability, DFT).

1. BSCAN Integration: Designate JTAG headers/test points on the PCB early. Use Boundary Scan (IEEE 1149.1) to test all digital net connectivity under BGAs, effectively turning a difficult physical test into a fast, digital one.
2. Coverage Target: Aim for ≥ 95% Structural Net Coverage (all nets reachable by ICT/Probe/BSCAN). Don't start manufacturing until coverage is quantified and approved.
3. TAKT Time Budget: The total test time (ICT + BSCAN + FCT) must be less than the required TAKT Time (the rate at which products must be produced). If test time is the bottleneck, you must split FCT (parallel test) or trim the scope of the structural checks.

Final Checklist: Test Strategy Mandates

Requirement	Metric / Goal	Action Mandate
Structural Coverage	≥ 95% of all accessible nets tested for opens/shorts.	Coverage report generated and approved by Quality Engineering (QE).
Hidden Joint Test	All BGAs/QFNs covered by BSCAN (for digital nets) or AXI sampling (for voids/HIP).	JTAG headers/test points must be placed on the PCB.
Test Route Design	Route choice (ICT vs. Flying Probe) based on projected volume and NRE payback.	Structural test must precede FCT to avoid wasting time on broken boards.
Throughput Control	Total Test Cycle Time ≤ TAKT Time.	If bottlenecked, FCT must be split into parallel stations or trimmed to core features.
Final Confidence	FCT must fully exercise all customer-facing features.	Power/safety checks (like rail voltage and current draw) run 100% of the time.