5.2 ICT & Fixture Design
In-circuit testing succeeds or fails on the strength of its fixture, where mechanics and electronics meet the PCB in a precise, repeatable handshake. A well-designed bed-of-nails not only delivers high coverage at speed but also protects the board from stress while surviving hundreds of thousands of cycles. Every detail—probe grid, tip selection, pad access, guarding, and backup support—determines whether measurements are clean or noisy, and whether the fixture is a quiet workhorse or a constant source of false failures. By pairing disciplined DFT on the PCB with robust fixture mechanics and regular maintenance, ICT becomes the most reliable structural gate in the line.
5.2.1 ICT in plain words (what the fixture must do)
An ICT fixture is a repeatable handshake between the tester and your PCB. It must:
- Touch the right nets (pads/vias/test points) reliably,
- Hold the board flat without cracking anything,
- Power up safely (when needed) and measure cleanly, and
- Survive hundreds of thousands of cycles with only light TLC.
Design the board for test first (DFT), then design the fixture so operators can’t not succeed.
5.2.2 Bed-of-nails basics (grids, counts, forces)
Support, support, support: lay out a backup pin field under large copper pours, BGAs, and the thinnest laminate regions so the board doesn’t oil-can when vacuum pulls down.
5.2.3 Probe tip menu (pick by surface & job)
Keep a probe legend in the fixture docs (part numbers, spring force, tip style, installed locations).
5.2.4 DFT keepouts & test-point rules (do this on the PCB)
- Reserve a grid: mark a 100 mil access grid early; avoid placing tall parts in the nail field you’ll need later.
- Test point spec: round ENIG pads preferred; open mask (no tent). Size per Section 11.2.2.
- Spacing & relief: keep ≥ 1.5 mm solder mask clearance around each test pad so tips don’t skate on gloss.
- Edge clearance: keep tall parts ≥ 5 mm from edges where vacuum seals ride; add tooling holes (3.0/3.2 mm) and global fiducials.
- Component keepouts under pressure posts: mark no-crush zones for electrolytics, crystals, wirewounds—give the fixture plate somewhere safe to push.
- High-current rails: add Kelvin pads (two close pads) for 4-wire resistance/IR drop checks.
- JTAG/BSCAN header/pads: plan chain order and a small header or robust pads (see 11.1 and 3.4).
Golden rule: one net = one reachable point (more for critical nets). Don’t rely on vias buried under parts unless you spec spear tips and access height.
5.2.5 Fixture mechanics (vacuum vs clamshell)
Vacuum (inline volume)
- Pros: fast, consistent force, great for conveyors; easy operator training.
- Cons: needs a gasket seal and a reasonably rectangular outline; sensitive to board bow and leaks.
Clamshell / pneumatic (flexible)
- Pros: loves odd shapes; top plates can “kiss” tall parts with soft foam standoffs; easy debug access.
- Cons: more moving parts; alignment and parallelism matter; cycle time slightly slower.
Always include
- Datum pins + tooling holes → repeatable X/Y/θ.
- Pressure plate with replaceable standoffs/foams → touches only designated topside keepouts.
- Pushback/strippers → keep the board from sticking to nails on release.
- Interlocks → no power unless fixture is closed and vacuum/air is good.
5.2.6 Electrical design (clean measurements, safe power)
- Guarding & shielding: for high-impedance or leakage tests, route guarded traces near sense nets; use shielded cables to the matrix.
- Kelvin for low ohms: use 4-wire on shunts, fuses, MOSFET Rds(on), and battery paths; place pads adjacent to reduce loop area.
- Power-on strategy: do power-off shorts/open checks first, then bring rails up through current-limited supplies with fast cut-off.
- Loads & relays: use solid-state where you can; keep relay coils away from tiny analog nodes; snub the inductive stuff.
- ESD discipline: ground the fixture frame; add wrist-strap posts; don’t turn your bed-of-nails into a static cannon.
5.2.7 Program & coverage (make the hardware earn its keep)
- Netlist compare: import CAD and run learned vs expected to catch mis-mapped nails.
- Structural first: opens/shorts/value/orientation → fast, nearly full coverage.
- Power-on next: rail presence, inrush/steady current, oscillator alive, reset behavior.
- BSCAN hooks: kick boundary-scan interconnect/pin toggles through the same fixture; program flash/MCU here to save FCT time.
- Guard-banding: crisp limits on Class-A risks (polarity, shorts); looser on passives where AOI already watches cosmetics.
5.2.8 Maintenance & reliability (fixtures like small rituals)
- Probe life: track hit counts; many pins last 100k–500k cycles depending on tip and surface. Replace by refdes group before they go noisy.
- Cleaning cadence: dry brush + vacuum daily; IPA swab for flux film weekly; never soak springs.
- Gaskets & seals: inspect monthly; leaks turn passes into flicker-fails.
- Pressure plate foams: replace when shiny/packed; they stop protecting parts when they stop springing back.
- Continuity self-test: a “fixture loopback” coupon proves harness/probe health before blaming boards.
- Spare kits: keep a probe kit (10% spares of every tip/force), gaskets, foams, pushers, springs.
5.2.9 Common pain → fast fixes
5.2.10 Release checklists (one for PCB, one for fixture)
PCB (DFT)
- Test pads per net (size per grid) with open mask, ENIG or good OSP
- Tooling holes + fiducials present; tall-part keepouts defined
- Kelvin pads on high-current/precision rails; JTAG/BSCAN pads/header placed
- Edge clearance for vacuum seals; pressure-post keepouts marked
Fixture
- Probe map matches CAD; backup pins under weak areas
- Tip styles/forces documented; spare kit stocked
- Gasket seals, pushers/strippers, interlocks verified
- Power-off → power-on sequence safe (current-limited)
- Self-test coupon passes; maintenance cadence posted