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5.3 Boundary Scan Essentials (JTAG)

Boundary scanScan, transformsformalized hiddenas digitalIEEE I/O1149.1 into(JTAG), accessible test points, giving visibility where probes cannot reach—especially under dense BGAs. By chaining devices through JTAG, manufacturers can detect interconnect faults, exercise buses, and even program silicon without adding extra pads or fixtures. A clean chain design, with clear ordering, solid signal integrity, and safe-state planning, makes boundary scanis a reliablemandatory and low-cost complement to ICT and flying probe. The result is higher coverage with fewer nails, faster programming, and more flexible test strategiestechnology for complexstructural boards.

5.3.1 What boundary scan is (plain language)

Thinktesting of JTAGhigh-density /Printed IEEECircuit 1149.1Boards (PCBs). It provides a digital solution to the physical access problem ascreated by modern area-array packages (BGAs, CSPs) where test pads are not viable. By building a tinyserial shift register (the boundary cell) into the pins of compliant Integrated Circuits (ICs), Boundary Scan allows the tester to digitally verify interconnectivity (opens and shorts) and conduct in-line device programming without requiring physical probes.

5.3.1 The JTAG Mechanism: Solving the Access Problem

Boundary Scan bypasses the need for physical probes by shifting control and observation logic directly onto the chip pins.

The Test Access Port (TAP)

Testing is controlled by the shift-registerTest Access Port (TAP), a dedicated interface on compliant ICs. The standard TAP uses four or five signals:

Signal

Function

TCK

Test Clock (synchronizes data)

TMS

Test Mode Select (controls state machine)

TDI

Test Data In (data shifted into the device)

TDO

Test Data Out (data shifted out for observation)

TRST

Test Reset (optional, asynchronous reset)

The Boundary Cell

Each digital pin on a compliant IC contains a boundary cell wrappedwhich aroundcan a chip’s I/O pins. You clockoperate in 1stwo modes:

  1. Normal Mode: The cell is transparent; the pin operates as intended.
  2. Test Mode: The cell disconnects the IC's core logic and 0stakes control of the pin, allowing the state (High/Low) to be set from TDI), the chip samples or drives pins, and you clock resultsread out (via TDO.

5.3.2 Strategic Value: Coverage and Programming

Boundary Scan excels where ICT is blind, making it the highest-value tool for verifying BGA structural integrity and device lifecycle management.

Strategic Advantage

Benefit

Impact on CoT/Throughput

Hidden Net Coverage

)Verifies structural integrity (opens, shorts, stuck-at-faults) under BGAs and other complex devices.

Eliminates the need for expensive, high-density test pads in BGA regions.

In-Line Programming

Programs on-board Flash, EEPROMs, and Microcontrollers (MCUs) through the JTAG chain.

Maximizes Throughput. Moves slow, serial programming cycles out of the time-critical FCT station (Chapter 5.1).

Diagnostic DoDepth

Pinpoints thatfaults to the specific pin/net level under a BGA.

Speeds up complex repair cycles; essential for managing high-cost component risk.

5.3.3 Design for Testability (DFT) Mandates

Successful Boundary Scan deployment requires non-negotiable planning during the PCB layout phase. The chain architecture cannot be fixed after fabrication.

  1. Chain Architecture: All JTAG-compliant devices (MCUs, FPGAs, complex processors) must be daisy-chained in a precise TDO-to-TDI sequence. This chain sequence must be defined, documented, and approved by the test engineering team early in the design cycle.
  2. TAP Interface: A dedicated JTAG header (often a 5-pin or 10-pin connector) or a specific pattern of test pads must be reserved on the PCB for the tester connection. This interface must be easily accessible by ICT or Flying Probe fixtures. 3. Termination and Buffering: The TCK and TRST lines must be properly terminated to minimize reflections and ensure reliable clocking across severallong chains. Buffers should be considered if the chain length exceeds standard limits to maintain signal integrity.
  3. Reset Control: The system's main reset line must be accessible and controllable during testing, often through the JTAG chain, to ensure the board enters a known initial state.

Final Checklist: JTAG Deployment

Requirement

Goal / Verification Point

Responsibility

Chain Architecture

All JTAG devices are daisy-chained and youthe can:TDO-to-TDI order is documented and locked.

Design

  • Engineer / Test interconnectsEngineer

Physical Access

Dedicated (opens/shorts)5-pin evenTAP underheader BGAs,or robust test pad arrangement is present.

PCB Layout must align with nothe bed-of-nailsfixture's onprobe thosegrid.

Coverage nets.

  • NudgeScope

    • BSCAN peripheralsis (via cluster tests)used to proveverify SPI/I²C wiring.

  • Program MCUs/SoCs/flash through the same port—often faster and cheaper than functional test programming.

    • You’ll hear four core signals: TCK, TMS, TDI, TDO (and sometimes TRST). One header, many wins.



    5.3.2 Chain design (rules that save you later)

    Make a clear, robust daisy chain. Order matters: TDI → [Device1] → [Device2] → … → [DeviceN] → TDO.

    Essential layout rules

    • Pulls:
      • TMS, TDI: pull-ups (≈10 kΩ typical).
      • TRST (if used): pull-down (≈10 kΩ) so the TAP stays in reset when idle.
      • Add a pull-up on nRESET/SRST if you route it to the header.
    • Series resistors (SI helpers): 22–68 Ω in TCK (and sometimes TMS) near the driver to tame ringing on long chains. Keep stubs short.
    • Levels: JTAG is voltage-domain specific. Expose a VTREF/VTG pin on the header (what the target I/O actually runs at) and buffer/level-shift if your pod needs it.
    • Header footprint: pick one, stick to it:
      • 2×5, 0.05" (ARM 10-pin)—compact, common, keyed.
      • 2×7, 0.1"—room for extras (nRESET, VTREF, GNDDetect).
      • Tag-Connect—no connector cost; pogo footprint only (great for volume).
         Place it near the chain’s first device to keep TCK short.
    • Chain options:
      • Put 0-Ω links or solder jumpers so you can bypass a device for debug or if a footprint is DNP in some variants.
      • Long chains (many devices) → consider JTAG buffer/re-driver or split into segments (link resistors decide which segment is in).
    • Power domains: if parts100% of the chaindigital can be unpowered, add isolation (series resistors or bus switches) so a dead device doesn’t clamp the chain. Tie TRST/nRESET so nothing wakes up “half-alive”.
    • Document the order: write the TDI→…→TDO list in the schematic and on the assembly drawing. Future-you will cheer.

    Bonus for speed: keep TCKinterconnects under ~150–200 mm total copper and avoid tees. If you must branch (multi-drop), keep branches very short and slow TCK in software.BGAs.



    5.3.3 Coverage with fewer nails (where BSCAN shines)

    BoundaryStructural scantest letscoverage youreport reduceconfirms ICTBGA padsnet on digital nets:coverage.

    • Interconnect test (1149.1): drive from Device A’s boundary cell, capture at Device B. Finds opens, bridges, stuck pins—under BGAs too.
    • Cluster tests: use a scannable device to bit-bang an I²C/SPI bus and read/write to non-scan parts (e.g., ADCs, sensors). Great for “are we wired?” without pads.
    • AC-coupled differential (1149.6): if you’ve got SERDES/AC caps, plan devices that support .6 or provide DC sense points upstream.

    WhereProgramming it doesn’t replace nailsTask

    • Pure

    analog paths, power inductors, op-amp loops—boundary cells can’t tell you gain/phase.

  • High-current nets—use Kelvin pads into ICT for resistance/IR drop.
  • Nets behind isolation/level shifters unless you can force test mode to make them transparent.

    • Strategy: aim for 95%+ structural coverage by mixing BSCAN + a trimmed ICT. Let ICT touch analog and power; let BSCAN own the BGAs and dense digital.



    5.3.4 Using JTAG forIn-line programming (make it fast & safe)

    Programming through the same header saves time and fixtures.

    Common flows

    • MCU/SoC JTAG/SWD: program internal flash or bootload external SPI flash through the core—fast.
    • FPGA JTAG: load configuration and sometimes flash (QSPI) via vendor tools.
    • Boundary-scan bit-bang to SPI flash: universal but slow; use only if the MCU/FPGA path isn’t available.

    Design for painless programming

    • Bring nRESET/SRST and VTREF to the header.
    • If programming off the SPI bus, give the programmer control: a series resistor (33–100 Ω) on CS and a hold/reset pin on the attached MCU so it releases the bus.
    • Add a boot-strap option (solder link) if the device needs to start in a programming-friendly mode.
    • Check current draw during program; some pods can’t source your whole board—plan aux power or keep loads off (jumpers, power switches).



    5.3.5 Safe states & “do no harm” list

    When tests run, your pattern generator can drive pins hard. Make it safe:

    • Define a board-level safe mode: all high-power drivers OE low, H-bridge IN low, backlight off, RF PAs disabled.
    • Off-board connectors: don’t blast GPIO into the customer’s world—tri-state or series-resistor protect anything that leaves the board.
    • Pulls win: ensure default pull-ups/downs put the board in a benign state before JTAG takes control.
    • For mixed-voltage chains, verify every boundary cell meets the I/O rating of whatFlash/MCUs it’sis touchingsuccessfully inexecuted testvia mode.the JTAG port.

    Test programming time is verified to be ≤ the required Takt Time.


    Golden Data


    5.3.6 Signal integrity that just works

    • KeepThe TCKBoundary shortest;Scan series-terminatingDescription itLanguage (33–68 Ω) cures most ringing.
    • Star grounds by the header; route TCK/TMS with ground reference; avoid running parallel to noisy clocks.
    • Very long chains or high TCK → add a JTAG buffer mid-chain.
    • If using ARM SWD on the same header, clearly mark pins and don’t cross clocks (SWDCLK vs TCK).



    5.3.7 Bring-up & debugging the chain (first day routine)

    1. Power on only the target domain; verify VTREF at the header.
    2. Run IDCODE scan: you should see each device’s ID in the order you drew.
    3. If scan stops halfway: check that device’s TRST/nRESET, its power rail, and TDO↔TDI jumpers. Use the 0-Ω bypass link to isolate.
    4. Import BSDLBSDL) files for eachall part;JTAG yourcomponents toolare maps which pins have boundary cellscollected and whicharchived.

    Files aremust input/output/3-state.

  • Run a short interconnect test on one bus first (e.g.,match the SPIexact lines),chip thenstepping scale.

    • Pro tip: keep a chain coupon (tiny PCB with known good chain and LEDs) to sanity-check pods/cables before blaming the board.



    5.3.8 Documentation that scales

    Bundle thisused in the Golden Data Pack:BOM.

    • Chain order (TDI→…→TDO), header pinout, VTREF.
    • Safe-state table (OE pins, rails to disable, boot straps).
    • BSDL list per device (exact silicon rev).
    • Programming recipes (tool, script, expected time).
    • Coverage report (nets under BSCAN vs ICT), so Quality knows how you hit SLA.


    5.3.9 Quick chooser (what to do on your design)

    • BGAs + tight access? → Prioritize BSCAN, trim ICT nails.
    • Lots of analog/power? → Keep ICT for those; use BSCAN for the digital glue.
    • Need fast programming? → Use MCU/FPGA debug path; avoid boundary-bit-bang unless nothing else exists.
    • Many ECOs expected? → BSCAN coverage + flying probe first; commit to an ICT fixture later.


    5.3.10 Pocket checklists

    Schematic & layout

    • TCK/TMS/TDI/TDO (±TRST) routed; pull-ups/downs placed
    • 2×5 (0.05") / Tag-Connect / 2×7 (0.1") header chosen; VTREF pinned out
    • 0-Ω bypass links / segment jumpers in chain; order documented
    • Isolation for unpowered domains; series resistors on noisy or shared lines
    • Safe-state pulls ensure benign behavior on power-up

    Test planning

    • BSDL files collected; toolchain imports clean
    • Interconnect & cluster tests defined (which buses to tickle)
    • Programming flow decided (MCU/FPGA vs boundary bit-bang) and timed
    • Mixed with ICT: who covers analog/power is explicit

    Bring-up day

    • IDCODE list matches chain order
    • Short interconnect test passes on one bus → then expand
    • Programming works from header; time within budget
    • Coverage report saved with the build



    When properly planned, boundary scan reduces fixture complexity, accelerates programming, and ensures structural confidence on designs that would otherwise be blind spots. This approach keeps costs in check while turning digital density into an advantage rather than a challenge.


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