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5.3 Boundary Scan Essentials

Chain design, test access reduction, and using JTAG for fast in-line programming—without making layout or test messy.

Boundary scan istransforms essentiallyhidden a built-in test bus that lets you check and controldigital I/O pins—ofteninto hiddenaccessible test points, giving visibility where probes cannot reach—especially under BGAs—withoutdense adding physical test pads.BGAs. By daisy-chaining devices through aJTAG, standard JTAG interface, youmanufacturers can detect opens,interconnect shorts,faults, andexercise stuck pins, bit-bang buses to talk to peripherals,buses, and even program MCUs,silicon FPGAs,without adding extra pads or flashfixtures. directlyA in-line. Goodclean chain design—clear device order, proper pull-ups/downs, short and well-terminated TCK routing, and isolation for unpowered domains—ensures reliability and speed. It works best when paireddesign, with ICTclear orordering, flyingsolid probesignal to cover analog, high-current,integrity, and non-scannable nets, allowing a reduction in fixture pins on dense digital designs. With the same header used for both test and programming, plus safe-state planningplanning, so nothing drives dangerously during patterns,makes boundary scan becomes a versatile,reliable and low-cost waycomplement to boostICT and flying probe. The result is higher coverage with fewer nails, faster programming, and streamlinemore productionflexible test,test especiallystrategies for BGA-heavycomplex boards.

5.3.1 What boundary scan is (plain language)

Think of JTAG / IEEE 1149.1 as a tiny shift-register wrapped around a chip’s I/O pins. You clock in 1s and 0s (TDI), the chip samples or drives pins, and you clock results out (TDO). Do that across several devices daisy-chained and you can:

  • Test interconnects (opens/shorts) even under BGAs, with no bed-of-nails on those nets.
  • Nudge peripherals (via cluster tests) to prove SPI/I²C wiring.
  • Program MCUs/SoCs/flash through the same port—often faster and cheaper than functional test programming.

You’ll hear four core signals: TCK, TMS, TDI, TDO (and sometimes TRST). One header, many wins.



5.3.2 Chain design (rules that save you later)

Make a clear, robust daisy chain. Order matters: TDI → [Device1] → [Device2] → … → [DeviceN] → TDO.

Essential layout rules

  • Pulls:
    • TMS, TDI: pull-ups (≈10 kΩ typical).
    • TRST (if used): pull-down (≈10 kΩ) so the TAP stays in reset when idle.
    • Add a pull-up on nRESET/SRST if you route it to the header.
  • Series resistors (SI helpers): 22–68 Ω in TCK (and sometimes TMS) near the driver to tame ringing on long chains. Keep stubs short.
  • Levels: JTAG is voltage-domain specific. Expose a VTREF/VTG pin on the header (what the target I/O actually runs at) and buffer/level-shift if your pod needs it.
  • Header footprint: pick one, stick to it:
    • 2×5, 0.05" (ARM 10-pin)—compact, common, keyed.
    • 2×7, 0.1"—room for extras (nRESET, VTREF, GNDDetect).
    • Tag-Connect—no connector cost; pogo footprint only (great for volume).
      Place it near the chain’s first device to keep TCK short.
  • Chain options:
    • Put 0-Ω links or solder jumpers so you can bypass a device for debug or if a footprint is DNP in some variants.
    • Long chains (many devices) → consider JTAG buffer/re-driver or split into segments (link resistors decide which segment is in).
  • Power domains: if parts of the chain can be unpowered, add isolation (series resistors or bus switches) so a dead device doesn’t clamp the chain. Tie TRST/nRESET so nothing wakes up “half-alive”.
  • Document the order: write the TDI→…→TDO list in the schematic and on the assembly drawing. Future-you will cheer.

Bonus for speed: keep TCK under ~150–200 mm total copper and avoid tees. If you must branch (multi-drop), keep branches very short and slow TCK in software.



5.3.3 Coverage with fewer nails (where BSCAN shines)

Boundary scan lets you reduce ICT pads on digital nets:

  • Interconnect test (1149.1): drive from Device A’s boundary cell, capture at Device B. Finds opens, bridges, stuck pins—under BGAs too.
  • Cluster tests: use a scannable device to bit-bang an I²C/SPI bus and read/write to non-scan parts (e.g., ADCs, sensors). Great for “are we wired?” without pads.
  • AC-coupled differential (1149.6): if you’ve got SERDES/AC caps, plan devices that support .6 or provide DC sense points upstream.

Where it doesn’t replace nails

  • Pure analog paths, power inductors, op-amp loops—boundary cells can’t tell you gain/phase.
  • High-current nets—use Kelvin pads into ICT for resistance/IR drop.
  • Nets behind isolation/level shifters unless you can force test mode to make them transparent.

Strategy: aim for 95%+ structural coverage by mixing BSCAN + a trimmed ICT. Let ICT touch analog and power; let BSCAN own the BGAs and dense digital.



5.3.4 Using JTAG for programming (make it fast & safe)

Programming through the same header saves time and fixtures.

Common flows

  • MCU/SoC JTAG/SWD: program internal flash or bootload external SPI flash through the core—fast.
  • FPGA JTAG: load configuration and sometimes flash (QSPI) via vendor tools.
  • Boundary-scan bit-bang to SPI flash: universal but slow; use only if the MCU/FPGA path isn’t available.

Design for painless programming

  • Bring nRESET/SRST and VTREF to the header.
  • If programming off the SPI bus, give the programmer control: a series resistor (33–100 Ω) on CS and a hold/reset pin on the attached MCU so it releases the bus.
  • Add a boot-strap option (solder link) if the device needs to start in a programming-friendly mode.
  • Check current draw during program; some pods can’t source your whole board—plan aux power or keep loads off (jumpers, power switches).



5.3.5 Safe states & “do no harm” list

When tests run, your pattern generator can drive pins hard. Make it safe:

  • Define a board-level safe mode: all high-power drivers OE low, H-bridge IN low, backlight off, RF PAs disabled.
  • Off-board connectors: don’t blast GPIO into the customer’s world—tri-state or series-resistor protect anything that leaves the board.
  • Pulls win: ensure default pull-ups/downs put the board in a benign state before JTAG takes control.
  • For mixed-voltage chains, verify every boundary cell meets the I/O rating of what it’s touching in test mode.



5.3.6 Signal integrity that just works

  • Keep TCK shortest; series-terminating it (33–68 Ω) cures most ringing.
  • Star grounds by the header; route TCK/TMS with ground reference; avoid running parallel to noisy clocks.
  • Very long chains or high TCK → add a JTAG buffer mid-chain.
  • If using ARM SWD on the same header, clearly mark pins and don’t cross clocks (SWDCLK vs TCK).



5.3.7 Bring-up & debugging the chain (first day routine)

  1. Power on only the target domain; verify VTREF at the header.
  2. Run IDCODE scan: you should see each device’s ID in the order you drew.
  3. If scan stops halfway: check that device’s TRST/nRESET, its power rail, and TDO↔TDI jumpers. Use the 0-Ω bypass link to isolate.
  4. Import BSDL files for each part; your tool maps which pins have boundary cells and which are input/output/3-state.
  5. Run a short interconnect test on one bus first (e.g., the SPI lines), then scale.

Pro tip: keep a chain coupon (tiny PCB with known good chain and LEDs) to sanity-check pods/cables before blaming the board.



5.3.8 Documentation that scales

Bundle this in the Golden Data Pack:

  • Chain order (TDI→…→TDO), header pinout, VTREF.
  • Safe-state table (OE pins, rails to disable, boot straps).
  • BSDL list per device (exact silicon rev).
  • Programming recipes (tool, script, expected time).
  • Coverage report (nets under BSCAN vs ICT), so Quality knows how you hit SLA.


5.3.9 Quick chooser (what to do on your design)

  • BGAs + tight access? → Prioritize BSCAN, trim ICT nails.
  • Lots of analog/power? → Keep ICT for those; use BSCAN for the digital glue.
  • Need fast programming? → Use MCU/FPGA debug path; avoid boundary-bit-bang unless nothing else exists.
  • Many ECOs expected? → BSCAN coverage + flying probe first; commit to an ICT fixture later.


5.3.10 Pocket checklists

Schematic & layout

  • TCK/TMS/TDI/TDO (±TRST) routed; pull-ups/downs placed
  • 2×5 (0.05") / Tag-Connect / 2×7 (0.1") header chosen; VTREF pinned out
  • 0-Ω bypass links / segment jumpers in chain; order documented
  • Isolation for unpowered domains; series resistors on noisy or shared lines
  • Safe-state pulls ensure benign behavior on power-up

Test planning

  • BSDL files collected; toolchain imports clean
  • Interconnect & cluster tests defined (which buses to tickle)
  • Programming flow decided (MCU/FPGA vs boundary bit-bang) and timed
  • Mixed with ICT: who covers analog/power is explicit

Bring-up day

  • IDCODE list matches chain order
  • Short interconnect test passes on one bus → then expand
  • Programming works from header; time within budget
  • Coverage report saved with the build



Bottom

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