1.5 Common Defects & Corrections
Bridging, icicles, skips—what causes them and how to eliminate them (with the smallest reliable change).
Most soldering defects—bridges, icicles, skips—come from a small set of causes: poor flux coverage, wrong top-side heat, unbalanced chip/main wave setup, or sloppy exits. Always check flux and preheat first, then change one setting at a time: chip wave for bridging, dwell/speed for fill, exit technique for icicles. Selective fixes are local (nozzle size, Z, path), while wave fixes are global (wave balance, angle, peel). Design tweaks—like correct hole sizes, thermal reliefs, and thief pads—remove chronic problems entirely. Measure results with photos and counts, save changes in the recipe, and avoid “big guess” adjustments. Small, targeted moves make defects vanish and keep them gone.
1.5.1 Triage first (don’t turn five knobs)
- Prep check (always first): flux coverage/dose and top-side temp at wave entry (1.2).
- Mechanics: pallet seals/clearances, finger cleanliness/angle (1.4.4), nozzle Z/height (1.3.6).
- Process knob: change one—speed/dwell, fountain height, chip↔main balance—then recheck on one panel.
1.5.2 Quick map (symptom → likely cause → smallest fix)
1.5.3 Root causes you can design out (next spin)
- Holes too tight / thin annular rings → undersized barrels never fill. Fix: lead Ø +0.20–0.45 mm (by thickness/copper), annular ≥0.25–0.30 mm, teardrops (1.1).
- No thermal reliefs to planes → cold joints. Fix: 4 spokes, 0.25–0.40 mm (1.1).
- Rows parallel to wave → long solder dams. Fix: rotate or add robber pads/pallet thieves (1.1, 1.4).
- SMT crowding miniwave → splash/bridges. Fix: 3–4 mm keepout or pallet masking (1.1, 1.3).
- Leads too long → icicles. Fix: plan protrusion 0.5–1.5 mm after solder (1.1).
1.5.4 Knob guide (change the right thing)
- Looks flooded / bridges early? → Flux & preheat first, then chip wave height/dwell.
- Looks starved / no top-fill? → Conveyor speed & dwell, then pot +5 °C.
- Exit looks stringy? → End-dwell + quick lift, small air/N₂ knife; don’t just raise temperature.
- Selective only on a few pins failing? → Local pass (spot dwell) and smaller nozzle, not global changes.
1.5.5 Mini playbooks (by defect)
A) Bridging (fine rows)
- Verify UV flux carpet and top-side in band (1.2).
- Raise chip 0.2–0.5 mm or +0.3 s dwell; keep main calm.
- Add end-dwell + kick; if still there → lower main 0.2 mm and add thief.
- Next rev: robber pad or pallet tail.
B) Poor top-side fill
- +5–10 °C top-side via preheat; slow belt or +0.3 s spot-dwell.
- Second light pass (drag or selective).
- If still low → +5 °C pot; check hole clearance/thermals for next spin.
C) Icicles on tabs/posts
- Faster exit; small knife.
- +5 °C pot; shorten dwell; confirm lead protrusion.
- For huge tabs: mini-dip or local spot dwell, not whole-board heat.
1.5.6 Selective vs wave: what’s different
- Selective fixes are local: nozzle Ø, Z touch-off, path speed/dwell, fountain height. Prefer two-stage passes (quick wet → slow finish).
- Wave fixes are global: chip↔main balance, conveyor angle, peel/knife. Don’t try to make main wave do chip’s job.
1.5.7 “Do not” list (saves days)
- Don’t raise pot temp to fix flux/preheat mistakes—spatter and oxidation follow.
- Don’t widen AOI limits for bridges; fix chip wave / exit.
- Don’t drown boards in flux; dry, even films beat puddles.
- Don’t tweak three settings at once—you lose the cause.
- Don’t accept “random non-fill” until you’ve checked hole size vs lead.
1.5.8 Tiny DOE when you’re stuck (3× panels)
- Factor A: Speed (−2 mm/s / nominal / +2 mm/s)
- Factor B: Fountain (−0.3 mm / nominal / +0.3 mm)
- Factor C: End-dwell (0 / +0.3 s)
Measure bridges/row, top-fill %, icicles. Keep the combo that improves the Pareto with the smallest heat.
1.5.9 Inspect what proves the fix
- Top-side barrel photos on the worst header (same pads each run).
- Count bridges per row, icicle length, skip rate on 3 panels before/after.
- Save settings in recipe comments (what you changed and why).
1.5.10 Pocket checklists
Before first article
- Flux pattern even; dose logged; no overspray
- Top-side temp at entry in band (per flux family)
- Chip and main heights set; angle 6–8°; finger path clean
- Selective: Z-zero taught; nozzle Ø sized to pad +1–2 mm
If bridging
- Add/extend chip; lower main a touch; end-dwell + kick
- Thief tail or pallet insert; re-photo same row
If non-fill / skips
- Slow belt or +0.3 s spot dwell; raise top-side 5–10 °C
- Second light pass; check hole/thermal design for next rev
If icicles
- Faster exit; light knife; +5 °C pot only if needed
- Verify lead protrusion; shorten dwell on tabs
Bottom line: most wave/selective defects are prep + first contact + exit problems. Keep flux thin and even, hit top-side activation, let the chip wave scrub and the main wave finish, then peel cleanly. Change one knob, verify on one panel, and write it down. That’s how defects disappear—and stay gone.