4.1 Functional Testing (FCT)

Functional testingTesting (FCT) is the provingfinal groundquality wheregate assembledthat hardwareverifies the completed Box Build unit meets reality.all Itspecified transformsperformance anrequirements. inertUnlike buildbasic intocontinuity aor verifiedHi-Pot productchecks, FCT simulates the product's intended operation, subjecting the unit to realistic electrical and communication loads. FCT provides the definitive Pass/Fail result that authorizes shipment and is the final opportunity to catch defects induced by applying power, simulating real-world conditions, and measuring performance against strict limits. More than just catching defects, it creates traceable records that link every measurement, recipe, and firmware version to the specificassembly unit,process making(e.g., reliabilityincorrect tangible.calibration, Byintermittent combiningconnections, disciplinedthermal power-up, realistic signal exercise, and locked test flows, functional testing becomes both a safety net and a shield against costly field failures.issues).

4.1.1 TheDefining missionthe (inFCT one line)Protocol

The FCT protocol must be comprehensive, repeatable, and automated to ensure maximum coverage and minimal human error.

A) Test Coverage and Goal

• Goal:Turn To exercise all primary functional domains of the product, including analog inputs, digital outputs, communication ports, power sequencing, and safety features.
• Stimulation: The tester must apply realistic stimuli (e.g., simulated sensor signals, power cycling) to verify the system responds correctly and within specified timing windows.
• Measurement: FCT must not only check for functionality (e.g., "Does the LED turn on?") but also measure performance (e.g., "Is the voltage output 12.0 V ± 0.1 V?").

B) Fixture Mandates

FCT requires a silent box into adedicated measured,test proven productfixture—apply powerdesigned safely,to exerciseinterface cleanly with the product's I/OO.

• Design: The fixture must use high-durability, test-grade connectors to withstand thousands of mating cycles without failure.
• Poka-Yoke: The fixture must be designed with realistickeying loads,or compareinterlocks againstto limits, and recordensure the truthunit tounder test (UUT) can only be placed in the serialcorrect number.orientation.

• Safety

  
  

  Interlocks:

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  Mandatory

  
  

  for high-power systems. The fixture must contain safety circuits that prevent the test from running if access panels are open or if the unit is not properly grounded.

4.1.2 Test flowFlow that keeps you safe (and fast)Execution

PlanFCT →is Powertypically →executed Exercisein →a Measurespecific →sequence Decideto →ensure Recordefficient troubleshooting and maximum defect detection.

A) Power-Up and Initial Checks

1. PlanSafety Ground: —The loadtest begins with a mandatory verification of the right recipe by SKU/Variantsafety ground connection scan;to fixtures/loadsthe ready.chassis (< 0.1 Ω), preventing damage or injury.
2. Power Sequencing: The tester verifies all power rails (e.g., 3.3 V, 5 V, 12 V) ramp up and stabilize in the correct sequence and within the specified voltage tolerance.
3. Communication Establishment: The tester verifies basic communication with the main processor (e.g., UART handshake, Ethernet link).

B) Functional and Configuration Checks

• External Interfaces: Verification of all external ports (USB, Ethernet, HDMI) using loopback dongles or certified test cables.
• PowerInternal Interfaces: —Verification safeof bring-upinterfaces between sub-assemblies (current-limit,e.g., sequencing)data withtransfer interlocks.between a main PCBA and a display module).
• ExerciseConfiguration: —The driveFCT interfacesis often the point where the product is fully configured: firmware loading, MAC address programming, and sensorscalibration likeof analog circuits (e.g., adjusting a potentiometer to meet a final output voltage target).

C) Final Verification

• Burn-In: For high-reliability products, FCT may include a burn-in or extended run-time test, subjecting the realunit world.to thermal stress to precipitate infant mortality failures (weak components or marginal solder joints) before shipment.
• MeasureData Logging: —All voltage,measured current,values timing,and comms,the thermalsfinal vs limits.
• DecidePass/Fail —status PASS/FAILmust bybe rulesautomatically logged and linked to the unit's Serial Number (noSN) “itin looksthe fine”MES (Manufacturing Execution System).

4.1.3 Managing FCT Failures

FCT failures represent the final process control audit and must trigger immediate corrective action.

A) Diagnosis and Rework

• Diagnosis: The FCT software must provide the technician with clear, actionable error messages (e.g., "FAIL: Power Rail 3.3V out of tolerance," or "FAIL: Port A, Pin 5 open circuit").
• RecordRework: —Units pushfailing results,FCT plots,must be routed to a dedicated rework station. Rework procedures must be strictly controlled, and versionsthe unit must return to FCT for a full re-test.MES

by

B) SN.
Data Analysis

Failure data must be analyzed immediately to identify trends.

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4.1.3 Fixture & station essentials

• InterlockedTrend lid, E-stop, bleed/dischargeIdentification: forA caps;sudden HV/HOT beacons.
• Mating connectors (prefer over pogo) sized for current; strain-relief for harnesses.
• Programmable PSU & loads (constant current/voltage/resistance; fast foldback).
• Sensors/actuators simulators: thermistors, 4–20 mA loops, relays/solenoids, encoders.
• Network hub with known-good links; RF attenuators or shield box if radios are checked.
• Calibration assets: DMM/clamps with current certs; station self-check at shift start.
• Recipe control: test script and limits selected by scan; block manual edits.
  

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4.1.4 Power-up sequence (don’t cook first)

• Visual pre-check: fans free, jumpers/config switches per SWI, no loose screws/FOD.
• Set limits: PSU current limit slightly above spec; electronic loads disabled.
• Apply rails in order (if required): e.g., 5 V → 12 V → 24 V; verify inrush < limit.
• Brownout test (quick): dip primary briefly; product should not latchincrease in a badspecific state.failure mode (e.g., "USB Port 2 Communication Fail") indicates a process drift (e.g., a harness is being incorrectly routed, or a fastener is damaging a connector) or a component batch failure.
• Thermal sniffCAPA:: 2–5FCT minutesfailure attrends idle;must fanstrigger spin;a noCorrective hotspotand beyondPreventive designAction expectations.(CAPA) process to fix the root cause on the assembly line, preventing further propagation of the defect.

Abort

Final if over-current trips, smoke/odor, abnormal noise. Quarantine with a ticket.

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4.1.5 Signals & interfaces (exercise like the real use)Checklist

InterfaceMandate	What to driveCriteria	WhatVerification to expectAction
DigitalTest I/OCoverage	ToggleProtocol outputs,exercises readall inputsfunctional withdomains pull-ups/downs(I/O, power, comms) and measures performance.	CorrectTest levels,specification timing,verified andagainst statethe transitionsproduct specification sheet.
AnalogSafety Check	ApplyFCT stepped/sweptbegins voltages/currentswith a mandatory safety ground verification (< 0.1 Ω).	ReadbackFixture linearityinterlocks withinprevent ±%high specvoltage/power tests if ground fails.
Motors/relaysAutomation	PWMTest steps,is start/stopfully cyclesautomated, repeatable, and linked to the MES.	CurrentAll profilesmeasured sane;values no(voltage, brownouts;current, flybackresistance) presentare logged against the unit SN.
Network (Eth/USB/Serial)Configuration	Enumerate,FCT ping/throughputincludes testfirmware loading and analog circuit calibration.	LinkTest up,log properconfirms speed,all dataconfiguration integritysteps were completed successfully.
StorageInfant Mortality	Read/write/SMARTBurn-in cycle (if specified) included to precipitate early-life failures.	CapacityThermal chamber logs verify the product was tested at the specified temperature and speed within limitstime.
Displays/LEDsFailure Response	TestFCT pattern,failures brightness/colortrigger immediate CAPA and routing to a dedicated rework station.	NoFailure stuckdata pixels;is correctimmediately color/levels
Sensors	Simulateanalyzed temp/pressure/etc.	Conversionfor tablesprocess correct;drift no jumps/glitchestrends.

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4.1.6 Performance checks (numbers that matter)

• Voltage drops under load at key test points (spec’d rails).
• Current draw: idle / typical / max; compare to golden.
• Timing: boot time, relay actuation delay, watchdog behavior.
• Throughput: network bandwidth, serial packet loss, USB speed.
• Thermals: ΔT at heatsinks after a brief load; fans meet RPM window.
• Noise (optional pre-compliance): ripple on rails, simple radiated sniff in fixture.
  

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4.1.7 Limits & golden references

• Limits live in the recipe, versioned and locked.
• Build golden unit data sets (current, drop, timings) at NPI and after ECOs; use tolerance bands (e.g., ±10%) unless the spec dictates absolute numbers.
• Separate spec limits (must meet) from golden trends (drift detection).
  

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4.1.8 Pass/fail logic (no vibes—just rules)

• Hard gates: safety, over-current, miswired I/O, failed storage, watchdog faults → FAIL.
• Measured gates: numeric compare to limit table → PASS only if all required rows pass.
• Retest rules: one immediate retest allowed only after a clear cause (fixture reseat, cable change). Second fail = NG-QUAR.
  

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4.1.9 Environmental sanity (fair tests)

• Log ambient Temp/RH; some limits vary with environment.
• If the spec requires warm-up or soak, the script enforces wait times.
• For radio checks, use a shielded mini-box or attenuators to avoid the open lab RF zoo.
  

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4.1.10 Data & traceability (what the record must contain)

Attach to the unit SN:

• Recipe ID & version, fixture ID, instrument IDs (cal status).
• Limits table used; operator and timestamp.
• For each test: stimulus (V/I/timing), measured values, PASS/FAIL, and plots where helpful (e.g., current vs time).
• Firmware image/hash, config/keys written, and results of any checksum verify.
• Photos if your SOP wants panel/label proofs at test.
  

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4.1.11 Throughput & ergonomics (takt-aware testing)

• Pre-stage two fixtures (ping-pong) if test time ≈ takt×2.
• Parallelize long soaks off the main lane (side rack) and return for closeout.
• Use quick-connects and guided nests; no raw pin probing.
• Make common failures obvious on the UI (red tile with the failing step, not a log file hunt).

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4.1.12 Starter test matrix (customize per product)

Group	Test	Typical limit
Safety	Earth bond (if applicable)	< 0.1 Ω
Power	Idle/Max current	Within spec ± tolerance
Thermal	Heatsink ΔT after 5 min @ load	≤ design value
Digital	GPIO read/write	100% map pass
Analog	ADC/DAC linearity	Error ≤ spec
Comm	Ethernet/USB/Serial	Link + throughput minimum
Storage	R/W speed, SMART	≥ threshold, no errors
UI	LEDs/display/buttons	Colors/levels/text correct
Watchdog	Induce stall	Recovers/reset per spec

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4.1.13 Acceptance cues (fast eyes)

Area	Accept	Reject
Power-up	No trip, currents stable	Repeated trips, audible arcing, smell
Fans/thermals	Spin; ΔT within band	Stalled fan, runaway ΔT
I/O	All endpoints respond	Dead port, wrong pin map
Networks	Enumerate/link	No link, flaky throughput
Storage	R/W pass	Errors, SMART warnings
Logs	Complete, bound to SN	Missing results, wrong recipe ID

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4.1.14 Common traps → smallest reliable fix

Trap	Symptom	Fix
Wrong recipe on right unit	Random fails	Scan-to-load recipe; block manual selection
Fixture intermittents	“Flaky” I/O	Use mating connectors; PM pogo pins; count cycles
Limits copied from old SKU	False PASS/FAIL	Versioned limit tables per SKU/Variant
No current limit at bring-up	Blown board	Always set PSU limit; staged rail enable
Operator edits logs	Audit pain	Write-once MES push; UI notes, not file edits
Long tests on main lane	Bottleneck	Side-loop soaks; ping-pong fixtures

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4.1.15 Pocket checklists

Before

• SKU/Variant scanned → correct recipe/limits loaded
• Fixture interlock/E-stop OK; instruments in cal
• Loads zeroed; PSU current limit set; fans clear

During

• Power-up clean; inrush OK; no alarms
• Exercise I/O per script; measure and log automatically
• Quick thermal sniff at load; fans meet RPM window

After

• PASS/FAIL decided by rules; no manual override
• Results, plots, firmware hash bound to SN
• NG units to QUAR/REWORK with failing step noted
  

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Consistently following this structured flow ensures every product leaves the line both safe and predictable. The payoff is quieter production, fewer escapes, and confidence that performance in the lab will hold steady in the field.