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4.1 Functional Testing

Functional testing is the proving ground where assembled hardware meets reality. It transforms an inert build into a verified product by applying power, simulating real-world conditions, and measuring performance against strict limits. More than just catching defects, it creates traceable records that link every measurement, recipe, and firmware version to the specific unit, making reliability tangible. By combining disciplined power-up, realistic signal exercise, and locked test flows, functional testing becomes both a safety net and a shield against costly field failures.

4.1.1 The mission (in one line)

Turn a silent box into a measured, proven product—apply power safely, exercise the I/O with realistic loads, compare against limits, and record the truth to the serial number.



4.1.2 Test flow that keeps you safe (and fast)

Plan → Power → Exercise → Measure → Decide → Record

  1. Plan — load the right recipe by SKU/Variant scan; fixtures/loads ready.
  2. Power — safe bring-up (current-limit, sequencing) with interlocks.
  3. Exercise — drive interfaces and sensors like the real world.
  4. Measure — voltage, current, timing, comms, thermals vs limits.
  5. Decide — PASS/FAIL by rules (no “it looks fine”).
  6. Record — push results, plots, and versions to MES by SN.


4.1.3 Fixture & station essentials

  • Interlocked lid, E-stop, bleed/discharge for caps; HV/HOT beacons.
  • Mating connectors (prefer over pogo) sized for current; strain-relief for harnesses.
  • Programmable PSU & loads (constant current/voltage/resistance; fast foldback).
  • Sensors/actuators simulators: thermistors, 4–20 mA loops, relays/solenoids, encoders.
  • Network hub with known-good links; RF attenuators or shield box if radios are checked.
  • Calibration assets: DMM/clamps with current certs; station self-check at shift start.
  • Recipe control: test script and limits selected by scan; block manual edits.



4.1.4 Power-up sequence (don’t cook first)

  • Visual pre-check: fans free, jumpers/config switches per SWI, no loose screws/FOD.
  • Set limits: PSU current limit slightly above spec; electronic loads disabled.
  • Apply rails in order (if required): e.g., 5 V → 12 V → 24 V; verify inrush < limit.
  • Brownout test (quick): dip primary briefly; product should not latch in a bad state.
  • Thermal sniff: 2–5 minutes at idle; fans spin; no hotspot beyond design expectations.

Abort if over-current trips, smoke/odor, abnormal noise. Quarantine with a ticket.


4.1.5 Signals & interfaces (exercise like the real use)

Interface

What to drive

What to expect

Digital I/O

Toggle outputs, read inputs with pull-ups/downs

Correct levels, timing, and state transitions

Analog

Apply stepped/swept voltages/currents

Readback linearity within ±% spec

Motors/relays

PWM steps, start/stop cycles

Current profiles sane; no brownouts; flyback present

Network (Eth/USB/Serial)

Enumerate, ping/throughput test

Link up, proper speed, data integrity

Storage

Read/write/SMART

Capacity and speed within limits

Displays/LEDs

Test pattern, brightness/color

No stuck pixels; correct color/levels

Sensors

Simulate temp/pressure/etc.

Conversion tables correct; no jumps/glitches


4.1.6 Performance checks (numbers that matter)

  • Voltage drops under load at key test points (spec’d rails).
  • Current draw: idle / typical / max; compare to golden.
  • Timing: boot time, relay actuation delay, watchdog behavior.
  • Throughput: network bandwidth, serial packet loss, USB speed.
  • Thermals: ΔT at heatsinks after a brief load; fans meet RPM window.
  • Noise (optional pre-compliance): ripple on rails, simple radiated sniff in fixture.



4.1.7 Limits & golden references

  • Limits live in the recipe, versioned and locked.
  • Build golden unit data sets (current, drop, timings) at NPI and after ECOs; use tolerance bands (e.g., ±10%) unless the spec dictates absolute numbers.
  • Separate spec limits (must meet) from golden trends (drift detection).


4.1.8 Pass/fail logic (no vibes—just rules)

  • Hard gates: safety, over-current, miswired I/O, failed storage, watchdog faults → FAIL.
  • Measured gates: numeric compare to limit table → PASS only if all required rows pass.
  • Retest rules: one immediate retest allowed only after a clear cause (fixture reseat, cable change). Second fail = NG-QUAR.


4.1.9 Environmental sanity (fair tests)

  • Log ambient Temp/RH; some limits vary with environment.
  • If the spec requires warm-up or soak, the script enforces wait times.
  • For radio checks, use a shielded mini-box or attenuators to avoid the open lab RF zoo.

4.1.10 Data & traceability (what the record must contain)

Attach to the unit SN:

  • Recipe ID & version, fixture ID, instrument IDs (cal status).
  • Limits table used; operator and timestamp.
  • For each test: stimulus (V/I/timing), measured values, PASS/FAIL, and plots where helpful (e.g., current vs time).
  • Firmware image/hash, config/keys written, and results of any checksum verify.
  • Photos if your SOP wants panel/label proofs at test.

4.1.11 Throughput & ergonomics (takt-aware testing)

  • Pre-stage two fixtures (ping-pong) if test time ≈ takt×2.
  • Parallelize long soaks off the main lane (side rack) and return for closeout.
  • Use quick-connects and guided nests; no raw pin probing.
  • Make common failures obvious on the UI (red tile with the failing step, not a log file hunt).


4.1.12 Starter test matrix (customize per product)

Group

Test

Typical limit

Safety

Earth bond (if applicable)

< 0.1 Ω

Power

Idle/Max current

Within spec ± tolerance

Thermal

Heatsink ΔT after 5 min @ load

≤ design value

Digital

GPIO read/write

100% map pass

Analog

ADC/DAC linearity

Error ≤ spec

Comm

Ethernet/USB/Serial

Link + throughput minimum

Storage

R/W speed, SMART

≥ threshold, no errors

UI

LEDs/display/buttons

Colors/levels/text correct

Watchdog

Induce stall

Recovers/reset per spec


4.1.13 Acceptance cues (fast eyes)

Area

Accept

Reject

Power-up

No trip, currents stable

Repeated trips, audible arcing, smell

Fans/thermals

Spin; ΔT within band

Stalled fan, runaway ΔT

I/O

All endpoints respond

Dead port, wrong pin map

Networks

Enumerate/link

No link, flaky throughput

Storage

R/W pass

Errors, SMART warnings

Logs

Complete, bound to SN

Missing results, wrong recipe ID



4.1.14 Common traps → smallest reliable fix

Trap

Symptom

Fix

Wrong recipe on right unit

Random fails

Scan-to-load recipe; block manual selection

Fixture intermittents

“Flaky” I/O

Use mating connectors; PM pogo pins; count cycles

Limits copied from old SKU

False PASS/FAIL

Versioned limit tables per SKU/Variant

No current limit at bring-up

Blown board

Always set PSU limit; staged rail enable

Operator edits logs

Audit pain

Write-once MES push; UI notes, not file edits

Long tests on main lane

Bottleneck

Side-loop soaks; ping-pong fixtures



4.1.15 Pocket checklists

Before

  • SKU/Variant scanned → correct recipe/limits loaded
  • Fixture interlock/E-stop OK; instruments in cal
  • Loads zeroed; PSU current limit set; fans clear

During

  • Power-up clean; inrush OK; no alarms
  • Exercise I/O per script; measure and log automatically
  • Quick thermal sniff at load; fans meet RPM window

After

  • PASS/FAIL decided by rules; no manual override
  • Results, plots, firmware hash bound to SN
  • NG units to QUAR/REWORK with failing step noted



Consistently following this structured flow ensures every product leaves the line both safe and predictable. The payoff is quieter production, fewer escapes, and confidence that performance in the lab will hold steady in the field.


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