2.1 Material Science, Stackups and Via Architecture

A printed circuit board defined solely by Gerber files is a suggestion, not a specification. Without an explicit material and stackup definition, fabrication houses will default to the lowest-cost laminate that meets the bare minimum IPC class, often resulting in signal integrity loss, warping during reflow, or conductive anodic filament (CAF) growth in the field. To guarantee reliability, the Golden Data Pack must lock the physical chemistry and geometry of the bare board before a single panel is cut.

Material Selection & Thermal Reliability

Select laminate materials based on the thermal stress of assembly and the operating environment, not just dielectric constant (Dk).

• If the assembly process is Lead-Free (SAC305) with multiple reflow cycles, Then specify High-Tg material (Tg ≥ 170˚C) to prevent barrel cracking.
• If the PCB operates in high-voltage or high-humidity environments, Then mandate Anti-CAF (Conductive Anodic Filament) materials.
• If the board requires high-reliability via structures, Then control the Z-axis Coefficient of Thermal Expansion (CTE) to ≤ 3.0% (50 – 260˚C) to match copper expansion rates.
• If rework is anticipated, Then ensure Decomposition Temperature (Td) is ≥ 340˚C to prevent delamination during hand soldering.

Stackup & Impedance Control

Do not rely on the fab's "standard" stackup. Define the layer buildup explicitly to control crosstalk, emissions, and signal return paths.

1. Impedance Models: Embed impedance requirements directly into the mechanical drawing or ODB++ data.
   • Single Ended: 50Ω ± 10% (Typical)
   • Differential Pair: 90Ω or 100Ω ± 10% (USB, PCIe, Ethernet)
2. Copper Balance: Maintain symmetrical copper distribution around the center of the stackup. Uneven copper weights (e.g., 1 oz on L1, 0.5 oz on L4) cause "potato chip" warping during reflow, leading to SMT placement failures.
3. Core vs. Prepreg: Define the construction.
   • If high-speed signals cross gaps, Then use low-Dk spread glass styles (e.g., 1067, 1078) to minimize fiber weave effect skew.

Pro-Tip: Avoid specifying specific laminate brands (e.g., "Isola 370HR") unless strictly necessary. Instead, specify the IPC-4101 slash sheet (e.g., /126) and performance parameters. This allows the fab to use equivalent verified stock without triggering an EQ.

Via Architecture & Aspect Ratios

Via reliability is a function of plating quality and aspect ratio (Board Thickness ÷ Drill Diameter). Exceeding standard ratios prevents adequate plating solution flow, resulting in thin copper knees and eventual open circuits.

Standard Constraints:

• Through-Hole Vias: Limit Aspect Ratio to 10:1 (e.g., 1.6 mm board requires ≥ 0.16 mm drill).
• Microvias (Blind): Limit Aspect Ratio to 0.8:1. Stacked microvias are high-risk; use Staggered microvias wherever possible to reduce stress concentration at the interface.
• Plating Thickness: Mandate IPC Class 2 average (20 µm) or Class 3 average (25 µm) internal plating thickness.

Validation & Evidence

Trust is not an engineering strategy. Require physical evidence from the fabrication house for every production lot.

1. Impedance Coupons: The fab must add test coupons to the panel waste rail.

• Action: Require a TDR (Time Domain Reflectometry) report matching the coupons to the specific batch.

2. Microsections (Cross-Sections):

• Action: Request a physical puck or high-res digital image of the microsection.
• Inspect: Check for Pink Ring (delamination), Wicking (copper migration along glass fibers), and actual Plating Thickness at the hole knee.

3. Solderability:

• Action: Ensure the surface finish (ENIG, OSP, HASL) passes wetting balance tests to prevent "Black Pad" or non-wetting during assembly.

Final Checklist