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3.4 FAI Build Evidence Pack and MP Release

First Article Inspection (FAI) is the forensic audit of the manufacturing process. It does not merely prove that a product can be built; it proves that the process is robust, repeatable, and statistically capable of scaling without exponential cost growth. The FAI Build Evidence Pack transforms the physical build event into data required for the "Go/No-Go" decision. Without this evidence, Mass Production (MP) is simply gambling with inventory.

The FAI Evidence Pack Requirements

The Evidence Pack must be a single, consolidated PDF or archive containing the following validated datasets. Do not accept scattered emails or verbal confirmations.

1. Yield Summary and Defect Pareto

Aggregate yield data to identify systemic weaknesses.

  • First Pass Yield (FPY): Report the percentage of units that passed all processes (SPI, AOI, X-Ray, ICT, FCT) on the first attempt without rework. High final yield with low FPY indicates a hidden cost structure.
  • Defect Pareto: Categorize top failure modes.
    • If Solder Bridges are top defect → Then review stencil aperture reduction and print pressure.
    • If Part Misalignment is top defect → Then review nozzle selection and vision recognition data.

2. The "As-Built" Configuration (Traceability)

NPI builds rarely match the initial documentation 100%. The Evidence Pack must capture the reality of the shop floor.

  • Redline BOM: Submit the Bill of Materials with clear markings showing any alternative components used, temporary substitutions, or value changes required to make the board work.
  • EQ/ECO Log: Compile all Engineering Queries (EQ) raised during the build and the resulting Engineering Change Orders (ECO).
  • Reflow Profile: Attach the measured thermal profile (temperature vs. time) overlaying the solder paste specification window.

3. Test and Programming Proof

  • Programming Verification: Provide a log summary confirming the correct checksum and firmware version were loaded.
  • Test Data: Submit parametric test results (voltage, current, frequency readings), not just Pass/Fail booleans. This establishes the baseline distribution (Cpk) for the product.

Pro-Tip: Do not accept "NFF" (No Fault Found) as a root cause during FAI. If a unit failed and then passed on retest, the test process itself is unstable. Label these as "Process Instability" and investigate fixture contact or tolerance.

The MP Release Gate

The transition from NPI to Mass Production is a formal "Gate Review." It requires a binary freeze of the Golden Data Pack.

Sign-off Authority:

Three signatures are mandatory to unlock MP:

  1. Manufacturing Engineering: Confirms process capability and fixture stability.
  2. Quality Assurance: Confirms critical dimensions and cosmetic standards are met (AQL).
  3. Product/Design Engineering: Confirms the device functions as intended.

The Frozen State:

Upon MP Release, the following elements become Read-Only:

  • Gerber/ODB++ Files.
  • Pick & Place Centroid Data.
  • The Approved Vendor List (AVL).
  • Test Limits and Firmware Checksums.

Any modification after this point requires a formal Process Change Notification (PCN).

Re-FAI Triggers

Continuous improvement is necessary, but uncontrolled changes introduce risk. Define clear triggers that invalidate the previous FAI and require a new qualification build.

Trigger Logic:

  • If a Critical Component (MCU, Sensor, PCB Laminate) changes manufacturer → Then perform Delta-FAI (partial qualification).
  • If production moves to a New Facility or SMT Line with different capabilities → Then perform Full FAI.
  • If the product has been dormant for ≥ 12 months → Then perform "Refresher" FAI to validate expired solder paste/components and machine settings.

Final Checklist

Parameter

Critical Requirement

Control Method

FPY Target

≥ 95% (or agreed target)

Auto-generated yield report

Documentation

100% match to "As-Built"

Redline BOM signed off

Defect Analysis

Root cause identified for Top 3

Pareto Chart & 8D Report

Process Window

Cpk ≥ 1.33 for critical tests

Parametric data analysis

Gate Status

Frozen configuration

MP Sign-off Document

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